AR# 53920


7 series GTX - placement failed after switching from Virtex-7 to Kintex-7


I am using a 7 series GTX. 

Previously I had a Virtex-7 design. 

When I try to migrate to Kintex-7, I see the below error.

Place:1415 - Unroutable Placement! A BUFDS / MMCM clock component pair have been found that are not placed at a routable BUFDS / MMCM site pair.
The BUFDS component <u_ten_gig/u_pcs_pma_gtx/ten_gig_eth_pcs_pma_block/gt_usrclk_source/ibufds_instQ1_CLK0> is placed at site <IBUFDS_GTE2_X0Y5>.
The corresponding MMCM component <u_ten_gig/u_pcs_pma_gtx/ten_gig_eth_pcs_pma_block/clkgen_i> is placed at site <MMCME2_ADV_X0Y4>.
The pair can use the fast path between them if the BUFDS and MMCM are both placed in the same clock region.
You may want to analyze why this problem exists and correct it. This placement is UNROUTABLE in PAR and therefore, this error condition should be fixed in your design.
You may use the CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message to a WARNING in order to generate an NCD file.
This NCD file can then be used in FPGA Editor to debug the problem.
A list of all the COMP.PINS used in this clock placement rule is listed below.
These examples can be used directly in the .ucf file to demote this ERROR to a WARNING.
   < PIN "u_ten_gig/u_pcs_pma_gtx/ten_gig_eth_pcs_pma_block/gt_usrclk_source/ibufds_instQ1_CLK0.O" CLOCK_DEDICATED_ROUTE = FALSE; >
   < PIN "u_ten_gig/u_pcs_pma_gtx/ten_gig_eth_pcs_pma_block/clkgen_i.CLKIN1"CLOCK_DEDICATED_ROUTE = FALSE; >




In Virtex-7 architecture, connection without a clock buffer is allowed if the IBUFDS_GTE2 and MMCM are located in the same clock region.

However, in Kintex-7, IBUFDS_GTE2 cannot drive MMCM clock inputs directly.

You will need to insert a BUFG or a BUFH in between.

AR# 53920
Date 12/09/2014
Status Active
Type General Article
Boards & Kits
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