AR# 53932


14.x - Timing - Do we have any documentation for Source Synchronous Serialization and Deserialization for Spartan-6 FPGA?


I am interfacing an Analog Devices AD9219 40 Msps ADC to our Spartan-6 LX45 FPGA.  The ADC outputs provide sample data by way of one source-synchronous LVDS clock and four LVDS DDR data lanes.  This is similar to how video pixel data is transmitted.  I have not been able to find a suitable reference design or application note.

Can I get any documentation,  application notes, or white papers?


Yes, there is a Application Note (XAPP 1064) available for this.

The Application Note can be found here:

AR# 53932
Date 08/06/2013
Status Active
Type General Article
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