AR# 53956


Vivado Synthesis - How do you extract a shift register and how do you control the threshold of the register chain depth for SRL inference?


This answer record explains the Vivado synthesis support of shift register extraction and control of the threshold or register required before a SRL is inferred.


Shift Register Extraction

Currently shift register extraction is only via HDL attribute. The UG 901 will be updated in 2013.1 with respect to shreg_extract syntax and usage.

Following VHDL/Verilog syntax examples as mentioned in XST will be supported by Vivado Synthesis,

VHDL example:

attribute shreg_extract : string;
attribute shreg_extract of {signal_name |entity_name }: {signal|entity} is "{yes|no},(true|false}";

Verilog Syntax example:

Placing before the module or signal declaration

(* shreg_extract = "{yes|no}, {true|false}" *)

However, there is a caveat. The SRL inference happens near the end of the synthesis flow. If the user sets the attribute on a module and this module is flattened, then the attribute is lost. So, it definitely works if you have flatten_hierarchy=none, but may not work for full or rebuilt. It is not difficult to tweak the code to make it work for the top level module, meaning if you set it on the top level module, it then works as a global switch.

Shift Register Threshold

Option 1

-shreg_min_size <value> is a global switch that sets the threshold for inference of SRLs. The default setting is 3. This value signifies the number of sequential elements after which the inference will result in SRLs specifically for static SRLs.

Option 2

Another option to disable this behavior is to apply attribute (* shreg_extract = "no" *) to the affected registers.

Option 3

Another option to disable this behavior is to apply a new attribute srl_style attribute (* srl_style = "register" *), introduced in 2013.3 to the affected signal/register. This will cause the tool to infer register instead of SRL.

AR# 53956
Date 10/25/2013
Status Active
Type Known Issues
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