AR# 53962

Description

Design Advisory Answer Records are created for issues that are important to designs currently in progress and are selected to be included in the Xilinx Alert Notification System: http://www.xilinx.com/support/myalerts.

This Design Advisory covers the Virtex-7 FPGA VC707 Evaluation Kit, including critical issues with the reference design delivered with the kit.

Solution

(Xilinx Answer 42944) - Design Advisory Master Answer Record for Virtex-7 FPGA
(Xilinx Answer 50906) - Design Advisory for Production Kintex-7 325T, 410T, 420T and Virtex-7 485XT - Bitstream compatibility requirements between GES and Production devices
(Xilinx Answer 53420) - Design Advisory for MIG 7 Series DDR3/DDR2 - Required calibration patch for v1.7 and v1.8
(Xilinx Answer 59167) - Design Advisory for MIG 7 Series DDR3 - Data rate specification changes for DIMM interfaces and data rate advisory for component interfaces

Revision History
6/3/2014 - Updated with 59167
1/25/2013 - Updated with 42944
1/24/2013 - Initial Release with Answer Record 50906, 53420

Linked Answer Records

Master Answer Records

Child Answer Records