Simulation errors occurs when simulating the IEEE 802.3 Multi-Channel 25G RSFEC core with Questa Sim.
The behavior of the core is incorrect and the example design simulation is failing.
This issue is related to Questa Sim inlining optimization for the encrypted design source.
To work around the issue, open the Elaboration tab in the Vivado Simulation Settings, and add '-inlineFactor=0' to the 'questa.elaborate.vopt.more_options' field.