How can I define the correct path for my Verilog "include" files with Vivado Synthesis?
The following methods can be used to define the location of an include file:
Project (GUI) mode:
Select Tools > Settings > General > Verilog options > Verilog Include Files Search Paths
This can be entered as a command line option by passing the -include_dirs option to the synth_design Tcl command.
"-include_dirs /home/project_1/include_directory/" - Full Path.
"-include_dirs ../../includes" - Relative Path from the name of the Synth folder (synth_1, synth_2 etc., whichever is applicable to the run) within the .runs directory.