UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!
Page Bookmarked
  1. Xilinx - All Programmable
  2. Support
  3. AR# 54020: Artix-7 FPGA AC701 Evaluation Kit - UG952 (v1.0) - Master UCF Bank 13 IOSTANDARDs are incorrect

AR# 54020

Artix-7 FPGA AC701 Evaluation Kit - UG952 (v1.0) - Master UCF Bank 13 IOSTANDARDs are incorrect

Description

UG952, AC701 Evaluation Board for the Artix-7 FPGA User Guide, includes the Master UCF in Appendix C. Bank 13 in this Master UCF has pins with IOSTANDARD=LVCMOS25 assigned to them; however, the VCCO for that bank is FPGA_1V8. What is the correct IOSTANDARD for pins in Bank 13?

Solution

Pins in Bank 13 of the AC701 should have the IOSTANDARD=LVCMOS18 assigned to them.

The Master XDC file has been corrected in UG952 (v1.1).

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
51900 Artix-7 FPGA AC701 Evaluation Kit - Known Issues and Release Notes Master Answer Record N/A N/A
AR# 54020
Date 02/01/2013
Status Active
Type General Article
Boards & Kits
  • Artix-7 FPGA AC701 Evaluation Kit