The "Input Example" figure is correct and the hold analysis is impacted by Clock Uncertainty.
The "Register-to-Register" figure is incorrect since it implies that these registers are sharing the same BUFG/BUFR/BUFIO component. When two synchronous elements are sharing the same clock network, then the hold analysis is not impacted by the Clock Uncertainty. If the two synchronous elements do not share the same clock network, then the Clock Uncertainty will impact the hold analysis.
| AR# 54071 | |
|---|---|
| Date | 01/31/2013 |
| Status | Active |
| Type | General Article |
| Tools |
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