UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 54165

LogiCORE IP Tri-Mode Ethernet MAC v5.5 - Vivado - Timing failure seen when core generated without address filter

Description

When using the Tri-Mode Ethernet MAC v5.5 in the Vivado tool flow, a failing timing path is seen when the address filter is not generated for the core.  

The path is:

  Source:               */trimac_top/TRI_SPEED.TRIMAC_INST/addr_filter_top/addr_regs.promiscuous_mode_reg_reg/C
                            (rising edge-triggered cell FDCE clocked by clkout1)
  Destination:         */trimac_top/TRI_SPEED.TRIMAC_INST/addr_filter_top/address_filter_inst/resync_promiscuous_mode/data_sync/D
                            (rising edge-triggered cell FDCE clocked by rx_clk )

Solution

This path can be covered by a max delay constraint.

The following XDC constraint can be added to cover the path:

set_max_delay -from [get_cells -hier -filter {name =~ *addr_filter_top/addr_regs.promiscuous_mode_reg_reg}] -to [get_cells -hier -filter {name =~ *addr_filter_top/address_filter_inst/resync_promiscuous_mode/data_sync}] 6 -datapath_only

This issue does not apply if the core is used in the ISE tool flow.

AR# 54165
Date Created 02/06/2013
Last Updated 09/22/2014
Status Active
Type General Article
IP
  • Tri-Mode Ethernet MAC