AR# 54165


LogiCORE IP Tri-Mode Ethernet MAC v5.5 - Vivado - Timing failure seen when core generated without address filter


When using the Tri-Mode Ethernet MAC v5.5 in the Vivado tool flow, a failing timing path is seen when the address filter is not generated for the core.  

The path is:

  Source:               */trimac_top/TRI_SPEED.TRIMAC_INST/addr_filter_top/addr_regs.promiscuous_mode_reg_reg/C
                            (rising edge-triggered cell FDCE clocked by clkout1)
  Destination:         */trimac_top/TRI_SPEED.TRIMAC_INST/addr_filter_top/address_filter_inst/resync_promiscuous_mode/data_sync/D
                            (rising edge-triggered cell FDCE clocked by rx_clk )


This path can be covered by a max delay constraint.

The following XDC constraint can be added to cover the path:

set_max_delay -from [get_cells -hier -filter {name =~ *addr_filter_top/addr_regs.promiscuous_mode_reg_reg}] -to [get_cells -hier -filter {name =~ *addr_filter_top/address_filter_inst/resync_promiscuous_mode/data_sync}] 6 -datapath_only

This issue does not apply if the core is used in the ISE tool flow.

AR# 54165
Date 09/22/2014
Status Active
Type General Article
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