When using the Tri-Mode Ethernet MAC v5.5 in the Vivado tool flow, a failing timing path is seen when the address filter is not generated for the core.
The path is:
(rising edge-triggered cell FDCE clocked by clkout1)
(rising edge-triggered cell FDCE clocked by rx_clk )
This path can be covered by a max delay constraint.
The following XDC constraint can be added to cover the path:
This issue does not apply if the core is used in the ISE tool flow.