2. Support
  3. AR# 5417: LogiCORE Direct Digital Synthesis (DDS) - What controls the effective Signal-to-Noise Ratio (SNR) of the DDS Core?
  4. AR# 54177: 2012.4 Vivado Implementation: Automatic insertion of BUFG on high fanout reset signals

AR# 54177

2012.4 Vivado Implementation: Automatic insertion of BUFG on high fanout reset signals

Description

The feature "Automatic insertion of BUFG in Vivado implementation on high fanout reset signals" is specified in the IRN (http://www.xilinx.com/support/documentation/sw_manuals/xilinx2012_4/irn.pdf ) on page 10.

  1. What is the fanout value after which the tool automatically inserts the BUFG?
     
  2. Can this threshold value be changed, and if yes, how?



Solution


1. The BUFG insertion on high fanout reset nets occurs during opt_design and depends on the following criteria:

  • Fanout greater than 50,000 set/reset loads where load pins are either R, S or clear or the load pin has attribute IS_CLEAR or IS_PRESET.
  • Design contains <= 12 BUFGs.

 2. The threshold is configurable with the following parameter:

set_param logicopt.thresholdBUFGinsertHFN value

The BUFG insertion can be disabled with the following parameter:

set_param logicopt.enableBUFGinsertHFN no 


AR# 54177
Date 03/23/2015
Status Active
Type General Article
Devices
Tools