The feature "Automatic insertion of BUFG in
Vivado implementation on high fanout reset signals" is specified in the IRN (http://www.xilinx.com/support/documentation/sw_manuals/xilinx2012_4/irn.pdf
) on page 10.
1. The BUFG insertion on high fanout reset nets
occurs during opt_design and depends on the following criteria:
2. The threshold is configurable with the following parameter:
set_param logicopt.thresholdBUFGinsertHFN value
The BUFG insertion can be disabled with the following parameter:
set_param logicopt.enableBUFGinsertHFN no
AR# 54177 | |
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Date | 03/23/2015 |
Status | Active |
Type | General Article |
Devices | |
Tools |