AR# 54190

Design Advisory for Zynq-7000 SoC, APU - L2 cache Operation Requires Programming of the slcr.L2C_RAM Register

Description

For proper L2 cache operation, the user code must program the slcr.L2C_RAM register (address 0xF800_0A1C) to the value of 0x0002_0202 before enabling the L2 cache. The reset value (0x0001_0101) might cause, very infrequently, the L2 cache to return invalid data.

Solution

It is up to the user code (FSBL or other user code) to set the slcr.L2C_RAM register to the value 0x0002_0202 before enabling the L2 cache.
Note: The L2 cache is disabled after reset and is not enabled by the BootROM.

Instructions for Xilinx EDK/SDK releases 14.4:

  1. Download the ZIP file at the end of this answer record.
  2. Extract the boot.s file to the Xilinx EDK/SDK installation directory (e.g., C:\Xilinx\14.4\ISE_DS\EDK).
  3. Verify that the boot.s file was written into the gcc directory (e.g., C:\Xilinx\14.4\ISE_DS\EDK\sw\lib\bsp\standalone_v3_08_a\src\cortexa9\gcc).

 

Affected systems: All systems using SDK 14.4 or earlier versions.

Resolution: This patch is scheduled to be integrated into a future SDK release. The register write can be added to any previous version of the software.

Note: The slcr.l2C_RAM register was previously reserved. It is added in the Zynq-7000 SoC Technical Reference Manual (TRM) v1.5 as "Reserved".

Attachments

Associated Attachments

Name File Size File Type
ar54190.zip 5 KB ZIP

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
47915 Design Advisory Master Answer Record for Zynq-7000 SoC Devices N/A N/A
AR# 54190
Date 05/28/2018
Status Active
Type Design Advisory
Devices