Version Found: v1.8
Version Resolved and other Known Issues: See (Xilinx Answer 40469)
Xilinx CORE Generator interface for 7 series Integrated Block Wrapper for PCI Express v1.8 core has only Initial ES and General ES options.
How do I generate the core intended for Artix-7 production silicon?
If targeting Artix-7 production silicon, it is required to have 2012.4 (14.4) device pack patch installed; the device pack will update the core for Artix-7 to include reset sequence described in (Xilinx Answer 53561). After the device pack is installed, all Artix-7 General ES and production silicon will need to use PCIe core version v1.8 with "General ES" selected from the core customization interface. The generated wrapper will work on both General ES and production silicon.
This "General ES" option in the core customization interface will be updated in a future tool release to avoid confusion between General ES and production silicon.
Artix-7 Initial ES will continue using the "Initial ES" selection.
The 2012.4 (14.4) device pack can be downloaded from xilinx.com -> Support -> Downloads -> Design Tools -> 2012.4-14.4:
http://www.xilinx.com/support/download/index.htm
Revision History
2/16/2013 - Initial release
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 40469 | 7 Series Integrated Block for PCI Express - Release Notes and Known Issues for All Versions up to Vivado 2012.4 and ISE 14.7 | N/A | N/A |
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 53561 | Design Advisory for Artix-7 FPGA GTP Transceivers: RX Reset Sequence Requirement for Production Silicon | N/A | N/A |
| AR# 54232 | |
|---|---|
| Date | 08/26/2013 |
| Status | Active |
| Type | General Article |
| IP |
|