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  3. AR# 5424: 1.5i Virtex Map - FATAL_ERROR:xvkma:xvkmap.c:587:1.112. Cannot find IOB attached to IBUFG
  4. AR# 54246: Design Advisory for 2012.3 and older Vivado Timing Analysis for 7 Series - Vivado Design Suite 2012.4 required for 7 Series timing analysis

AR# 54246

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Design Advisory for 2012.3 and older Vivado Timing Analysis for 7 Series - Vivado Design Suite 2012.4 required for 7 Series timing analysis

Description

This Design Advisory was most recently updated on February 14th, 2013 with the following details:

The Vivado Design Suite 2012.3 and older versions were under-reporting delays on some of the longer paths of a device for 7 series designs.  

The timing engine and speed files were updated in Vivado Design Suite 2012.4 to address this situation, which can cause the TNS and WNS (timing scores) to increase.

Solution

The following is an overview of the steps to take to review the impact of this change on your design in Vivado Design Suite 2012.4 and newer versions:

  1. Assess timing analysis results for an increase in the WNS and TNS (timing scores)
  2. Update the failing designs


Details:

1.  Assess timing analysis results for an increase in the TNS and WNS (timing scores)
 
    A.  Run the design through timing analysis using Vivado Design Suite 2012.4 or newer version.
         For example: 'report_timing -max_paths 12'

    B.  If the design passes timing analysis with no errors, no further action is necessary.
         Designs in the field are not affected by this change if timing analysis has passed.
         Designs in progress should continue to use the latest Vivado Design Suite 2012.4/2013.x for further development.
     
    C.  If the design fails timing analysis, the design must be updated so that it passes timing analysis and a new bitstream must be generated.

    2.  Update the failing design:

    A.  Vivado Project-full flow (GUI Users)
        • Option 1: Re-run the Implementation steps. If timing analysis passes with the newly routed design, continue to bitstream creation.
        • Option 2: Re-run the Synthesis and Implementation steps. If timing analysis passes with the newly routed design, continue to bitstream creation.
    B.  Vivado Project-less flow (Command Line Users)
        • Option 1: Re-run route_design. If timing analysis passes with the newly routed design, continue to bitstream creation
        • Option 2. Re-run place_design and route_design.  If timing analysis passes with the newly routed design, continue to bitstream creation.

    Linked Answer Records

    Master Answer Records

    Answer Number Answer Title Version Found Version Resolved
    40835 Design Advisory for Xilinx Timing Solution Center N/A N/A

    Associated Answer Records

    Answer Number Answer Title Version Found Version Resolved
    50906 Design Advisory for Production Kintex-7 325T, 410T, 420T and Virtex-7 485XT, 690XT, 1140XT - Bitstream compatibility requirements between GES and Production devices N/A N/A
    AR# 54246
    Date 10/17/2014
    Status Active
    Type Design Advisory
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