AR# 54249


IP Release Notes and Known Issues for LogiCORE RXAUI for Vivado 2013.1 and newer tool versions


This answer record contains the Release Notes and Known Issues for the RXAUI Core and includes the following:

  • General Information
  • Known and Resolved Issues
  • Revision History

This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2013.1 and forward.
The last supported Vivado release of the RXAUI core is version 4.4 (Rev. 6) in Vivado 2019.1.

Please reference XTP025 - IP Release Notes Guide for past known issue logs and ISE support information.



General Information

Supported devices can be found in the following three locations:

For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado design tools.

Version Table

This table correlates the core version to the first Vivado design tools release version in which it was included.

Core VersionVivado Tools Version
v4.4 (Rev. 6)2019.1
v4.4 (Rev. 5)2018.3
v4.4 (Rev. 4)2018.2
v4.4 (Rev. 3)2018.1
v4.4 (Rev. 2)2017.4
v4.4 (Rev. 1)2017.3
v4.3 (Rev.7)2017.1
v4.3 (Rev.6)2016.4
v4.3 (Rev.6)2016.3
v4.3 (Rev.5)2016.2
v4.3 (Rev.4)2016.1
v4.3 (Rev.3)2015.4
v4.3 (Rev. 2)2015.3
v4.3 (Rev. 1)2015.2
v4.2 (Rev. 3)2014.4
v4.2 (Rev. 2)2014.3
v4.2 (Rev. 1)2014.2
v3.0 (Rev. 1)2013.2

General Guidance

The table below provides answer records for general guidance when using the LogiCORE IP RXAUI core.

Answer RecordTitle
(Xilinx Answer 38279)Ethernet IP Solution Center
(Xilinx Answer 55077)Ethernet IP Cores - Design Hierarchy in Vivado
(Xilinx Answer 55078)RXAUI Shared Clocking and Reset Logic
(Xilinx Answer 55079)RXAUI Debug Interface

Known and Resolved Issues

The following table provides known issues for the RXAUI core, starting with v3.0, initially released in the Vivado 2013.1 tool.

Note: The "Version Found" column lists the version the problem was first discovered.

The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Answer RecordTitleVersion FoundVersion Resolved
(Xilinx Answer 71455)This core is being deprecated and will no longer be available starting in Vivado 2019.2v4.4 (Rev. 6)NA
(Xilinx Answer 70255)RXAUI v4_4 :Resetdone is not completed on RX in UltraScale and UltraScale+ devicesv4.4v4.4 (Rev. 2)
 UltraScale - GTRXRESET required after entering or exiting GT Near-end PMA loopbackv4.0v4.3
(Xilinx Answer 62354)GTRXRESET toggles when using transceiver debug PRBS inputsv4.0v4.3
(Xilinx Answer 62351)7 Series - GTP and GTH - Simulation not supported with UNIFAST model or SIM_GTRESET_SPEEDUPv4.0NA
(Xilinx Answer 59914)Additional XDC constraints for the MDIO signal inputs to ease timing closurev4.1v4.2
(Xilinx Answer 59292)7 Series - TX Phase Alignment state machine not reset on falling edge of powerdownv4.0v4.2
(Xilinx Answer 59861)7 Series GTP- Production reset DRP sequence could get in hung state that requires reconfiguration to recoverv4.0v4.2
(Xilinx Answer 59860)7 Series GTP - Update to hold off further resets to GTs during reset_in_progressv4.0v4.2
(Xilinx Answer 58083)Update to 7 Series GTX Transceiver attribute - RXDFEXYDENv2.4v4.0
(Xilinx Answer 56313)Update to 7 Series GTP reset logicv3.0 (Rev. 1)v4.0
(Xilinx Answer 55840)RXAUI v3.0 - Update to RX termination for 7 Series GTP and GTH Transceiversv3.0v3.0 (Rev. 1)
(Xilinx Answer 55900)Verilog - If using TXPRBSFORCEERR input, the connection to GT1 in Verilog needs to be correctedv3.0v3.0 (Rev. 1)
(Xilinx Answer 55229)Artix-7 - Critical Warning - No cells match DRP path for false path constraintv3.0v3.0 (Rev. 1)
(Xilinx Answer 55009)7 Series GTX/GTH/GTP Transceivers - TX Sync Controller Change for Phase Alignment in Buffer Bypass Modev2.4v3.0
(Xilinx Answer 53561)Artix-7 - RX Reset Sequence Requirement for Production Siliconv2.4v3.0
(Xilinx Answer 50848)7 Series GT Transceivers - Updates may be needed to GT wrapper filesv2.4v3.0


Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
55078 RXAUI v3.0 - 2013.1 - Shared Clock and Reset Logic N/A N/A

Child Answer Records

Associated Answer Records

AR# 54249
Date 12/09/2020
Status Active
Type Release Notes
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