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AR# 54274

Zynq-7000 Example Design - IPI AXI3 Master


This design connects a custom AXI3 master to each of the Zynq AXI slaves: AXI_HP0-3, AXI_GP0-1, and AXI_ACP. The custom core performs a simple incrementing value memory test to DDR. The error bits are routed to the GPIO; failures occur if any bit is set to '1'.

Note: AXI4 masters are recommended for new designs instead of AXI3. The AXI3 master in this design is used to demonstrate the highest frequencies to the Zynq-7000 AXI interfaces.

Note: An Example Design is an answer record that provides technical tips to test a specific functionality on Zynq-7000. A tip can be a snippet of code, a snapshot, a diagram or a full design implemented with a specific version of the Xilinx tools.  It is up to the user to "update" these tips to future Xilinx tools releases and to "modify" the Example Design to fulfill his needs. Limited support is provided by Xilinx on these Example Designs.


Implementation Details
Design Type PS & PL
SW Type None
PL Cores AXI Register Slice
Boards/Tools zc702
Xilinx Tools Version Vivado 2013.1, build 0212
Other details Design closes timing at 250 MHz.
Address Map
Base Address
axi3_master_hp0 0x10000000
axi3_master_hp1 0x11000000
axi3_master_hp2 0x12000000
axi3_master_hp3 0x13000000
axi3_master_gp0 0x14000000
axi3_master_gp1 0x15000000
axi3_master_acp 0x16000000
PS GPIO  Error bits
Files Provided
xilinx.com_user_axi3_master_1.0.zip Custom AXI3 master.

Block Diagram


commands to load design via XMD.

 Block Diagram




  1. Extract the zip to a directory, create a zc702 project, and then add the directory as a repository preference.
  2. From the Tcl Console, 'source ar54274_bd.tcl' after creating a blank zc702 project and adding repository.
  3. Generate Bitstream.
  4. File -> Export to SDK.
  5. Place xmd.ini into exported SDK directory, change to that directory, and run xmd. This will load and start the design.
  6. In XMD, 'mrd 0xE000A068' to check the status of the Error bits.


Associated Attachments

Name File Size File Type
ar54274_bd.tcl 11 KB TCL
xilinx.com_user_axi3_master_1.0.zip 11 KB ZIP
xmd.ini 423 Bytes INI
AR# 54274
Date Created 02/14/2013
Last Updated 08/01/2013
Status Active
Type General Article
  • Zynq-7000
Boards & Kits
  • Zynq-7000 All Programmable SoC ZC702 Evaluation Kit