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AR# 54350

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7 Series - FRAME_ECCE2 port decriptions and functionality

Description

How can I use the FRAME_ECCE2 in 7 Series devices?

Solution

The 7 series FPGA Frame ECC logic detects single or double bit errors in configuration frame data. It uses a 13-bit Hamming code parity value that is calculated based on the frame data generated by BitGen. 

During readback, the Frame ECC logic calculates a syndrome value using all the bits in the frame including the ECC bits. If the bits have not changed from the original programmed values, SYNDROME[12:0] are all zeros. If a single bit has changed, including any of the ECC bits, the location of the bit is indicated by SYNDROME[11:0]. If two bits have changed, SYNDROME[12] is 0 and the remaining bits are non-zero. If more than two bits have changed, SYNDROME[12:0] are indeterminate. 

The error output of the block is asserted if one or two bits have changed. To use the Frame ECC logic, the FRAME_ECC _VIRTEX6 primitive must be instantiated in the users design, and readback must be performed using SelectMAP, JTAG, or ICAP interfaces.

At the end of each frame of readback, the syndrome_valid signal is asserted for one cycle of the readback clock (CCLK, TCK, or ICAP_CLK). The number of cycles required to read back a frame varies with the interface used. Repairing bits that have changed requires a user design. The FRAME_ECCE2 logic does not repair changed bits. The design must be able to store at least one frame of data or be able to fetch original frames of data for reload. 

The simplest operation is as follows:

  1. A frame is read out through ICAP and stored in block RAM. The frame address is generated as each frame is read.
  2. If an error is indicated by the error output of the FRAME_ECC block, the readback is halted and the SYNDROME value is saved.
    If SYNDROME[12] is 0 and SYNDROME[11:0] are non zero, the whole frame must be restored. If SYNDROME[12] is 1, SYNDROME[11:0] is used to locate the error bit in the saved frame.
  3. The repaired frame is then written back into the frame address generated in step 1.
  4. Readback then resumes on the next frame address.

Pin NameTypeDescription
SYNDROMEVALIDOutputFrame ECC syndrome valid pulse. Active one cycle for each frame. Used to sample ERROR and SYNDROME[12:0].
ECCERROROutputWhen SYNDROMEVALID is active, this output indicates if a frame error was detected or not:

  • ERROR=1 when SYNDROME[12:0] is non-zero.
  • ERROR=0 when SYNDROME[12:0] is all zeros.
SYNDROME[12:0]Output

When SYNDROMEVALID is active, this output reflects the frame error condition:

  • No bit error: [12]==0, [11:0] ==0
  • One bit error: [12]==1, [11:0] !=0
  • Two bit errors: [12]==0, [11:0] != 0
  • More than two bits: SYNDROME is unpredictable
  • Parity Bit Error: [12]==1, [11:0]==0
CRCERROROutputRBCRC error. See (UG470), Chapter 8 Readback CRC
FAR[25:0]OutputFrame Address Register Value.

  • SEU Correction/Injection and ICAP applications can benefit from being able to see the FAR register.
  • This output can point to the EFAR or FAR configuration register depending on the FARSRC attribute.
SYNWORD[6:0]OutputOut Word address of error.

  • The index (0? -> 80) of the 32-bit word in the frame where an ECC error has been detected. Decoded from SYNDROME.
  • Valid when ECCERRORSINGLE is High.
SYNBIT[4:0]OutputBit address of error.
  • The index (0 -> 31) of the bit w/ error in the word pointed to by SYNWORD in the frame detected.
  • Valid when ECCERRORSINGLE is High.
ECCERRORSINGLEOutputIndicates a single-bit Frame ECC error detected

For SSIT devices the FRAME_ECCE2 is available on all SLRs. The user should place and use the components to detect ECC on each SLR.

If only a single FRAME_ECC is included in the design and not placed, it will be placed in the Master SLR.

AR# 54350
Date 12/02/2016
Status Active
Type General Article
Devices
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