This is correct behavior.
The "-rename_top" option of the "write_verilog" command only works with "-mode funcsim/timesim".
The default option for write_verilog is "-mode design".
For the VHDL command "write_vhdl", the default mode option is "-mode funcsim" so with the same command parameters, the tool will rename the entity/module:
"write_vhdl -rename_top <new_entity_name> <HDL_netlist>.vhdl".
| AR# 54359 | |
|---|---|
| Date | 12/11/2014 |
| Status | Active |
| Type | General Article |
| Tools |
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