AR# 54367

Description

This answer record contains the Release Notes and Known Issues for the Aurora 8B10B Core and includes the following:

• General Information
• Known and Resolved Issues
• Revision History
  

This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2013.1 and forward.
Please refer to XTP025 - IP Release Notes Guide for past known issue logs and ISE support information.

Aurora 8B/10B LogiCORE IP Page:

https://www.xilinx.com/content/xilinx/en/products/intellectual-property/aurora8b10b.html

Solution

General Information

Supported devices can be found in the following three locations:

• Aurora 8B10B LogiCORE IP Product Guide
• Aurora 8B10B LogiCORE IP Page - https://www.xilinx.com/content/xilinx/en/products/intellectual-property/aurora8b10b.html
• Open the Vivado tool -> IP Catalog, right-click on an IP and select Compatible Families.

For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado tools.

Changes in v11.1 Rev5:

• Bug Fix: Fixed display only issue showing improper clock frequencies for tx_out_clk and sync_clk in IP Integrator flow for GTP devices 
  
• Revision change in one or more subcores
  

Changes in v11.1 Rev4:

• Bug Fix: Fixed the default tie-off values for rxlpmen port as per INS_LOSS_NYQ and RX_EQ_MODE selection
• Bug Fix: Fixed a bug that generated unexpected error messages during re-customization of IP in IP Integrator
• Other: Added support for Artix-7 XA7A12TCPG238/CSG325 and XA7A25TCPG238/CSG325 devices
• Revision change in one or more subcores

• General: Added support for CPG238 packages in XC7A12T, XC7A12Ti, XC7A25T, XC7A25Ti, XC7Z012S devices
• Revision change in one or more subcores

Changes in v11.1 Rev2:

• General: GTP attribute update in XC7A12T, XC7A12Ti, XC7A25T, XC7A25Ti, XC7Z012S devices
• General: Standard CC logic is enabled after lane-up itself instead of waiting till channel-up condition
• General: Added optional parameter C_DOUBLE_GTRXRESET to assert additional reset for handling errors during lane initialization in duplex links with very high PPM differences
• General: Updated display values of RX_TERMINATION_PROG_VALUE for UltraScale+ devices to match Xilinx UltraScale Architecture Transceivers user guides
• Revision change in one or more subcores

Changes in v11.1 Rev1:

• Bug Fix: Unused gtrxresetseq DRP signals removed from TX-simplex based designs
• Other: UltraScale GT Wizard version upgrade.

Changes in v11.1: 

• New Feature: UltraScale GT Wizard Instance can be brought out of Aurora IP for UltraScale devices
• Revision change in one or more subcores
  

Changes in v11.0 (Rev7):

• General: Added support for XC7A12T, XC7A12Ti, XC7A25T, XC7A25Ti devices
• Revision change in one or more subcores 

Changes in v11.0 (Rev6):

• Bug Fix: Fixed issue involving failure in validate BD design in IP Integrator due to the floating point precision difference of gt_refclk
• Bug Fix: Fixed TXDIFFCTRL and DMONITOROUT port widths for UltraScale devices in IP symbol
• Feature Enhancement: Added Advanced RX GT Options selection in the GUI
• Other: Added support for XC7A12T, XC7A12Ti, XC7A25T, XC7A25Ti, XC7Z012S devices
• Revision change in one or more subcores
  

Changes in v11.0 (Rev5):

• Fixed Artix-7 periodic channel up toggle issue - refer to (Xilinx Answer 66963)
• Revision change in one or more subcores

Changes in v11.0 (Rev4):

• Fixed the preserving Equalizer selection issue when additional transceiver ports option is enabled
• Adjusted line rate and associated frequency limits for -1,-1H,1HV,-1L,-1LV, -2LV speed grade devices to match UltraScale FPGAs Data Sheet
• Revision change in one or more subcores

Changes in v11.0 (Rev3):

• Added support for new speed grades of XQ7K325T and XQ7K410T devices
• Added support for new speed grades of XQ7Z030, XQ7Z045 and XQ7Z100 devices
  
• Added support for new speed grade of XQ7A050T, XQ7A100T and XQ7A200T devices
• Revision change in one or more subcores
  

Changes in v11.0 (Rev. 2):

• Updated RTL to fix CDC warnings
• IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instance

Changes in v11.0 (Rev1):

• Added support for XQ7VX690T, XQ7Z045 and XQ7Z100 devices
• BUFG removed on DRP Clock input
• TXPMARESETDONE used in rxstartupfsm for GTP RX-only Simplex configuration
• set_false_path constraint on synchronizers updated

Changes in v11.0:

• Added support for 7 Series devices with FFV and FBV Pb-Free (ROHS) packages
• Added txinhibit and pcsrsvdin optional transceiver control and status ports
• Both reset and gt_reset ports made asynchronous to the core
• Standard CC module made part of IP, do_cc and warn_cc ports removed
• Flow control ports grouped into AXI4 Stream interface
• Control and status ports are grouped as display interfaces
• Added support for single ended clocking option to INIT_CLK and GTREFCLK
• Added support for contiguous lane selection for UltraScale devices
• CRC resource utilization optimized
• GT Reference Clocks, User Clock and Sync Clock ports updated with expected frequency values in IP-Integrator
• Line rate value restricted to 4 decimal digits for UltraScale devices
• INIT clock frequency value restricted to 6 decimal digits

• UltraScale GT Wizard version updated

• Added support for new XC7A15T, XC7A15TI, XA7A15T, XC7A35TI, XC7A50TI, XC7A75TI, XC7A100TI and XC7A200TI devices
• Added support for XC7Z015I, XC7Z030I, XC7Z045I, XC7Z035, XC7Z035I and XC7Z100I devices
• Added support for XC7K160TI, XC7K325TI, XC7K355TI, XC7K410TI, XC7K420TI and XC7K480TI devices
• BUFG added to DRP Clock input
• Line rate range for -2L speed grade 1.0V Artix devices updated to 6.25Gbps
• Location constraint changed for Xilinx Evaluation platform boards

Changes in v10.3:

• UltraScale GT Wizard version updated
• Added support for new UltraScale devices
• Added support for XQ7A50 devices
• Added support for XA7Z030 devices
• Added support for user configurable DRP clock and INIT clock through IP GUI
• Added C_EXAMPLE_SIMULATION parameter for post synthesis/implementation simulation speedup
• set_max_delay constraint changed to set_false_path constrains to destination flops
• XDCs compliant with updated timing constraining guidelines
• Added support for Xilinx Evaluation platform boards
• User selectable option enabled for GT DRP interface in IPI systems
• Added support for auto propagate to INIT and DRP clock in IPI systems
• Fixed gt_dmonitorout_out data width mismatch issue for Zynq devices
• Differential INIT clock input added to UltraScale example design
• Addressed CPLL power down circuit requirement for 7 Series Transceivers - refer to AR
• GT startup fsms updated to be compliant with 7 Series GT Wizard
• Addressed update to GTH/GTP Production RX reset sequence implementation - refer to AR
• Parameter declaration issue with IES simulator addressed

• UltraScale GT Wizard version change
• Added support for XQ7Z045 RF900 devices
• Fixed hold violation timing issues in UltraScale device based designs
• Updated channel bonding levels logic for >= 13 lanes in 4 byte mode
• Fixed gt0_dmonitorout_out port width for GTX devices in transceiver debug ports
• Free running INIT CLK is connected to VIO core in example design
• Fixed latch inference issue in CRC modules for VHDL designs
• Updated CLK_COR_MIN_LAT and CLK_COR_MAX_LAT values for 16-GT (GTHE3_CHANNEL) in UltraScale device.
  

Change in v10.2:

• Added support for UltraScale devices
• Added support for XC7Z015, XC7A50T, XC7A35T devices
• Added support for automotive Artix XA7A35, XA7A50T, XA7A75T & XA7A100T devices
• Enhanced support for IP Integrator
• Added Little endian support for data & flow control interfaces as non-default GUI selectable option
• Fixed VHDL syntax issue on rxpmaresetdone_t signal for 7 Series based designs
• Updated OOC XDC with all the available clocks for the selected IP configuration
• Fixed TXCRC and RXCRC modules to operate upon valid data and report correct CRC status
• Updated core reset logic with tx_lock synchronization
• Updated the simplex timer values for 7 Series production silicon logic updates
• Updated the hot-plug logic to handle clock domain crossing efficiently
• Added recovery mechanism for channel bonding failure

Change in v10.1:

• Increased the number of optional transceiver control and status ports

Change in v10.0:

• Added support for XC7A75T device
• Added startup FSM integration for 7 Series FPGA GT reset sequence
• Added GUI option to include or exclude Vivado lab tools support for debug
• Updated line rate for Artix-7 wire bond package devices for speed grade -2 and -3
• Added GUI option to include or exclude shareable logic resources in the core. For details, refer to Migrating section of Product Guide - pg046-aurora-8b10b.pdf
• Added optional transceiver control and status ports - Refer to pg046-aurora-8b10b.pdf
• Updated synchronizers for clock domain crossing to reduce Mean Time Between Failures (MTBF) from meta-stability
• Reduced warnings in synthesis and simulation
• Added support for Cadence IES and Synopsys VCS simulators
• Added support for IP Integrator level 0

Version Table

This table correlates the core version to the first Vivado design tools release version in which it was included.

General Guidance

The table below provides answer records for general guidance when using the LogiCORE IP Aurora 8B10B core.

Revision History