2. Support
  3. AR# 5439: M1.5i EPIC - Cannot edit block/CLB/macro, even in read-write mode.
  4. AR# 54398: Zynq-7000 SOC - When using a faster DDR device than the clock frequency, which timing specifications can be used?

AR# 54398

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Zynq-7000 SOC - When using a faster DDR device than the clock frequency, which timing specifications can be used?

Description

When using a faster speed grade DDR device with a slower clock for PS DDRC, which specification should I use? The faster or slower one?

Solution

If the DDR device mentions it is back compatible with the slower speed grade, the specifications of both speed grades are available to be used.

To achieve maximum bandwidth, EDK XPS selects the better setting to generate ps7_init for inclusion into the FSBL. 

For more information on proper settings, contact the device vendor, and override with a custom setting in the Xilinx tools.

AR# 54398
Date 05/28/2018
Status Active
Type General Article
Devices
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