AR# 54421


LogiCORE IP AXI UART Lite - Release Notes and Known Issues for Vivado 2013.4 and older tool versions


This answer record contains the Release Notes and Known Issues for the AXI UART Lite and includes the following:

  • General Information
  • Known and Resolved Issues
  • Revision History

This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2013.4 and older tool versions.
Please reference XTP025 - IP Release Notes Guide for past known issue logs and ISE support information.



General Information

Supported devices can be found in the following three locations:

For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado.

Version Table

This table correlates the core version to the first Vivado design tools release version in which it was included.

Core Version Vivado Tools Version
2.0 2013.4
2.0 2013.1
1.02.a 2012.4

General Guidance

The table below provides answer records for general guidance when using the LogiCORE AXI UART Lite.

Answer Record Title
(Xilinx Answer 55248) Vivado Timing and IP Constraints
(Xilinx Answer 35863) EDK, UART Lite - How do I clear a UART Lite interrupt?
(Xilinx Answer 35903) 12.1 EDK, UART Lite - Why do UART errors rates increase with higher baud and lower clock frequencies?

Known and Resolved Issues

The following table provides known issues for the AXI UART Lite, starting with v2.0, initially released in the Vivado 2013.1 tool.

Note: The "Version Found" column lists the version the problem was first discovered.

The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

There are no known issues for the Vivado 2013.4 tool.

Revision History
04/03/2013 - Initial release
12/18/2013 - Updated for 2013.4
AR# 54421
Date 03/19/2015
Status Active
Type Release Notes
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