This answer record contains the Release Notes and Known Issues for the Zynq Processing System 7 IP and includes the following:
This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2013.4 and older tool versions.
Please reference XTP025 - IP Release Notes Guide for past known issue logs and ISE support information.
Zynq Processing System 7 IP Page:
Supported devices can be found in the following three locations:
For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado.
This table correlates the core version to the first Vivado design tools release version in which it was included.
The table below provides answer records for general guidance when using the Zynq Processing System 7 IP.
|(Xilinx Answer 55248)||Vivado Timing and IP Constraints|
|(Xilinx Answer 52538)||Zynq-7000 SoC - Boot and Configuration|
|(Xilinx Answer 54740)||14.4 XPS - Zynq SoC 32 bit peripherals connected to the HP port are not working when using XMD flow.|
Known and Resolved Issues
The following table provides known issues for the Zynq Processing System 7 IP, starting with v5.3, initially released in the Vivado 2013.4 tool.
Note: The "Version Found" column lists the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
|(Xilinx Answer 54740)||Zynq SoC HP port width is not getting set correctly to 32 bits; instead, it defaults to 64 bits||14.5||N/A|
|(Xilinx Answer 51207)||When creating a BOOT.bin file with a bitstream that does not have processing_system7, the system does not boot||14.5||N/A|
|12/18/2013||Updated for 2013.4|
|07/11/2013||Under General Information, removed link to Product Guide and replaced it with a general link to Processing System 7 Documentation|