AR# 54453

Description

This answer record contains the Release Notes and Known Issues for the AXI Interconnect Core and includes the following:

• General Information
• Known and Resolved Issues
• Revision History

• axi_clock_converter
• axi_crossbar
• axi_data_fifo
• axi_register_slice

The AXI Interconnect version 2.0 and later is composed of the individual sub-modules above, and is currently only available in IP Integrator.

This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2013.1 and newer tools.
Please reference XTP025 - IP Release Notes Guide for past known issue logs and ISE support information.

LogiCORE AXI Interconnect Core IP Page:
http://www.xilinx.com/content/xilinx/en/products/intellectual-property/axi_interconnect.html

Solution

General Information

Supported devices can be found in the following three locations:

• LogiCORE AXI Interconnect Core Product Guide (v2.0)
• LogiCORE AXI Interconnect Core IP Page
• Open the Vivado tool -> IP Catalog, right-click on an IP and select "Compatible Families"

For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado.

Version Table

This table correlates the core version to the first Vivado design tools release version in which it was included.

General Guidance

The following table provides answer records for general guidance when using the LogiCORE IP AXI Interconnect core.

Known and Resolved Issues

The following table provides known issues for the AXI Interconnect core, starting with v1.06a, initially released in Vivado 2012.4 design tools.

Note: The "Version Found" column lists the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History
05/27/2013 - Initial release
12/09/2013 - Updated versions