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  4. AR# 54473: LogiCORE IP CPRI Core - Release Notes and Known Issues for Vivado 2013.1 and newer tool versions

AR# 54473

LogiCORE IP CPRI Core - Release Notes and Known Issues for Vivado 2013.1 and newer tool versions

Description

This answer record contains the Release Notes and Known Issues for the CPRI LogiCORE IP and includes the following:

  • General Information
  • Known and Resolved Issues
  • Revision History

This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2013.1 and newer tool versions.

Please reference XTP025 - IP Release Notes Guide for past known issue logs and ISE support information.

CPRI LogiCORE IP Page:

https://www.xilinx.com/content/xilinx/en/products/intellectual-property/do-di-cpri.html

Xilinx Forums: 

Please seek technical support via the Networking Connectivity Board. The Xilinx Forums are a great resource for technical support. 

The entire Xilinx Community is available to help here, and you can ask questions and collaborate with Xilinx experts to get the solutions you need.

Solution

General Information

Supported devices can be found in the following three locations:

CPRI Hardware Demonstration Designs

KC705, VC709, ZC706, AC701, KCU105, VCU108, VCU118 and ZCU102 boards are supported by CPRI Demonstration Designs.

They can be accessed through the CPRI Member Lounge :

https://www.xilinx.com/member/cpri_eval/index.htm

For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado design tools.

Version Table

This table correlates the core version to the Vivado design tools release version, compatible CPRI Spec version, and the Change Log Answer Records

Core VersionVivado Tools Version CPRI Spec VersionVivado IP Change Log IP Patch
v8.112019.2v7.0(Xilinx Answer 72923)
v8.102019.1v7.0(Xilinx Answer 72242)
v8.9(Rev 2)2018.3v7.0(Xilinx Answer 71806)
v8.9 (Rev 1)2018.2v7.0(Xilinx Answer 71212)
v8.92018.1v7.0(Xilinx Answer 70699)(Xilinx Answer 71517)
v8.8 (Rev 1)2017.4v7.0(Xilinx Answer 70386)
v8.82017.3v7.0(Xilinx Answer 69903)
v8.7 (Rev 3)2017.2v7.0(Xilinx Answer 69326) (Xilinx Answer 71370)
v8.7 (Rev 2)2017.1v7.0(Xilinx Answer 69055)
v8.7 (Rev 1)2016.4v7.0(Xilinx Answer 68369)(Xilinx Answer 68427)
v8.72016.3v7.0(Xilinx Answer 68021)
(Xilinx Answer 68426)
v8.6 (Rev 1)2016.2v7.0(Xilinx Answer 67345)(Xilinx Answer 68300)
v8.62016.1v7.0(Xilinx Answer 66930)
v8.5 (Rev 1)2015.4v6.1(Xilinx Answer 66004)(Xilinx Answer 68282)
v8.52015.3v6.1(Xilinx Answer 65570)
v8.4 (Rev 1)2015.2v6.0(Xilinx Answer 65077)
v8.42015.1v6.0(Xilinx Answer 64619)
v8.3 (Rev.2)2014.4.1v6.0(Xilinx Answer 63724)
v8.3 (Rev.1)2014.4v6.0(Xilinx Answer 62882)
v8.32014.3v6.0(Xilinx Answer 62144)
v8.2 (Rev.1)2014.2v6.0(Xilinx Answer 61087)
v8.22014.1v6.0(Xilinx Answer 59986)
v8.12013.4v5.0(Xilinx Answer 58670)
v8.02013.3v5.0(Xilinx Answer 58605)
v7.02013.1v5.0

 

Known and Resolved Issues

The following table provides known issues for the CPRI LogiCORE IP, starting with v7.0, initially released in Vivado 2013.1.

Note: The "Version Found" column lists the version the problem was first discovered.

The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Answer RecordTitleVersion
Found		Version
Resolved
(Xilinx Answer 71517)CPRI 8.9 - inconsistent latency through the 4 channel Hard FEC wrapper IP core running at 24.3 Gbps line ratev8.9v8.9 Rev 2
(Xilinx Answer 71369)CPRI 8.9 - Link resyncs every 10ms when IQ RX is looped back to IQ TX v8.9v8.9 Rev2
(Xilinx Answer 71379)CPRI v8.7 (Rev 3) - The reference clock frequency on 10.1G FEC enabled line rate is incorrectv8.7 rev3v8.9
(Xilinx Answer 70210)CPRI v8.7 (Rev 3) -  9.8G line rate frequency on the output rxrecclkout is not correct v8.7 rev3v8.9
(Xilinx Answer 71115)CPRI v8.8 Rev 1 - pcs_rxdata_chX are "x" when running example design simulation v8.8 rev1v8.9
(Xilinx Answer 70385)CPRI v8.8 - Patch Update, GTY support for xcku15p ffva1760 and ffve1760 v8.8v8.8 rev1
(Xilinx Answer 69056)CPRI v8.7 Rev 2 - 64b/66b scrambling not enabled on FEC line ratesv8.7 rev2v8.7 rev3
(Xilinx Answer 68530)CPRI v8.7 Rev 1 - For some UltraScale and UltraScale+ devices, the RX and TX output clocks are not correctly constrained if cores are generated with the 9.830G and under line rate option. v8.7 rev1v8.7 rev2
(Xilinx Answer 68529)CPRI v8.7 Rev 1 - In cores supporting the 24,330.24 Mbps line rate, scrambling is not supported at the 8B10B encoded line rates. v8.7 rev1v8.7 rev2
(Xilinx Answer 68510)CPRI v8.7 Rev 1 - 64b66b control block is encoded incorrectlyv8.5 rev1v8.7 rev2
(Xilinx Answer 67215)CPRI v8.6 - Software Reset bit 31 in General Configuration and Transmit Alarms register does not clear when the CPRI core is using shared logic from another CPRI core.
v8.4v8.6 rev1
(Xilinx Answer 66971)CPRI v8.5 Rev1 - CPRI auto-negotiation can hang using the CPLL in UltraScale transceivers v8.5rev1v8.6
(Xilinx Answer 64739)CPRI v8.4 - Why do I see incorrect behavior when I use transceiver debug pins to access UltraScale DRP ports? v8.4v8.5
(Xilinx Answer 60818)CPRI v8.2 - [Vivado 12-1387] No valid object(s) found for set_max_delay constraintv8.2v8.3
(Xilinx Answer 62510)CPRI v8.1 - Ethernet eth_rx_frame_count number is stuck sometimes.v8.1v8.2 rev2
(Xilinx Answer 55952)CPRI v7.0 - MMCM Output Clock Changesv7.0v8.0
(Xilinx Answer 57046)CPRI v7.0 - AXI Ports from CPRI do not match IPI external Portsv7.0v8.3
 

General Guidance

The table below provides known issues and design advisory for the FPGA Transceiver when using the CPRI LogiCORE IP.

Answer RecordTitle
(Xilinx Answer 57487)UltraScale FPGA Transceiver Wizard - Release Notes and Known Issues for Vivado 2013.4 and newer versions
(Xilinx Answer 59294)Design Advisory for 7 Series GT wizard - CPLL causes power spike on power up for 7 Series GTs**
(Xilinx Answer 53561)Design Advisory for Artix-7 FPGA GTP Transceivers: RX Reset Sequence Requirement for Production Silicon
(Xilinx Answer 53779)Design Advisory for Virtex-7 FPGA GTH Transceiver - RX Reset Sequence Requirement for Production Silicon
(Xilinx Answer 55009)Design Advisory for 7 Series GTX/GTH/GTP Transceivers - TX Sync Controller Change for Phase Alignment in Buffer Bypass Mode


** (Xilinx Answer 59294) details a possible power up issue for 7 Series GT transceivers. A work-around will be included in the CPRI core in the 2014.3 release.

To avoid this issue please ensure that a reference clock is present for the transceiver when the device is powered up at line rates of 6144Mbps and below.

Revision History

09/07/2018Added 71369, 71370,71379 and 71517
06/08/2018Added 70210
05/10/2018Added 71115
01/15/2018Added 70385
04/19/2017Added 69056
01/16/2017Added 68529 and 68530
01/10/2017Added 68610
05/23/2016Added 67215
04/06/2016Added 66971
02/25/2016Added 66402
01/14/2016Added CPRI spec version
06/15/2015Added 64739 and 62510
02/28/2015Added 63622
02/28/2015Added 57487
09/03/2014Added 59294
05/27/2014Added 60818
12/03/2013Added 55952
04/03/2013Initial release

Linked Answer Records

Child Answer Records

Answer Number Answer Title Version Found Version Resolved
53561 Design Advisory for Artix-7 FPGA GTP Transceivers: RX Reset Sequence Requirement for Production Silicon N/A N/A
53779 Design Advisory for Virtex-7 FPGA GTH Transceiver - RX Reset Sequence Requirement for Production Silicon N/A N/A
55009 Design Advisory for 7 Series FPGA GTX/GTH/GTP Transceivers - TX Sync Controller Change for Phase Alignment in Buffer Bypass Mode N/A N/A
55952 CPRI v7.0 - MMCM Output Clock Changes N/A N/A
60818 CPRI v8.2 - [Vivado 12-1387] No valid object(s) found for set_max_delay constraint with option '-from [get_cells -hier -filter {name =~ *cpri_i/cpri_options.cpri_i/rx_modules_I/RX_HFNSYNC_10G.rx_hfnsync_i/hfnsync_reg}]'. N/A N/A
59294 Design Advisory GT wizard - CPLL causes power spike on power up for 7 series GTs N/A N/A
62510 LogiCORE CPRI v8.1 - Ethernet eth_rx_frame_count number is stuck sometimes. N/A N/A
64739 CPRI v8.4 - Why do I see incorrect behavior when I use transceiver debug pins to access UltraScale DRP ports? N/A N/A
57046 2014.4 Vivado IP Integrator - AXI ports from Vivado CPRI do not match IP Integrator AXI external ports N/A N/A
66971 CPRI v8.5 rev1 - CPRI auto-negotiation can hang when using the CPLL in UltraScale transceivers N/A N/A
67215 CPRI V8.6 - Software Reset bit 31 in General Configuration and Transmit Alarms register does not clear when the CPRI core is using shared logic from another CPRI core. N/A N/A
68529 CPRI v8.7 (Rev 1) - In cores supporting the 24,330.24 Mbps line rate, scrambling is not supported at the 8B10B encoded line rates. N/A N/A
68530 CPRI v8.7 (Rev 1) - For some UltraScale and UltraScale+ devices, the RX and TX output clocks are not correctly constrained if cores are generated with the 9.830G and under line rate option. N/A N/A
69056 CPRI v8.7 Rev 2 - 64B/66B scrambling not enabled on FEC line rates. N/A N/A
70385 CPRI v8.8 - Patch Update, GTY support for xcku15p ffva1760 and ffve1760 N/A N/A
69646 XPE - Certain power rails do not change with temperature or process change, why? N/A N/A
71115 CPRI v8.8 Rev 1 - pcs_rxdata_chX are "x" when running example design simulation N/A N/A
70210 CPRI v8.7 (Rev 3) - 9.8G line rate frequency on the output rxrecclkout is not correct N/A N/A
71370 CPRI v8.7 (Rev 3) - Patch update for CPRI v8.7 (Rev 3) in Vivado 2017.2 N/A N/A
71369 CPRI 8.9 - Link resyncs every 10ms when the IQ RX is looped back to the IQ TX N/A N/A
71517 CPRI v8.9 - Patch Update for Hard FEC Wrapper latency Issue in Vivado 2018.1 N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
36969 LogiCORE IP CPRI - Release Notes and Known Issues N/A N/A
AR# 54473
Date 11/27/2019
Status Active
Type Release Notes
IP