This answer record contains the Release Notes and Known Issues for the Discrete Fourier Transform (DFT) LogiCORE IP and includes the following:
This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2013.1 and newer tool versions.
Please reference XTP025 - IP Release Notes Guide for past known issue logs and ISE support information.
Discrete Fourier Transform (DFT) LogiCORE IP Page:
https://www.xilinx.com/content/xilinx/en/products/intellectual-property/dft.html
General Information
Supported Devices can be found in the following three locations:
For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado design tools.
Version Table
This table correlates the core version to the first Vivado design tools release version in which it was included.
| Core Version | Vivado Tools Version |
|---|---|
| v4.0(Rev. 15) | 2018.1 |
| v4.0(Rev. 14) | 2017.4 |
| v4.0(Rev. 14) | 2017.3 |
| v4.0(Rev. 13) | 2017.2 |
| v4.0(Rev. 13) | 2017.1 |
| v4.0(Rev. 12) | 2016.4 |
| v4.0(Rev. 12) | 2016.3 |
| v4.0(Rev. 11) | 2016.2 |
| v4.0(Rev. 11) | 2016.1 |
| v4.0(Rev. 10) | 2015.4 |
| v4.0(Rev. 9) | 2015.3 |
| v4.0(Rev. 8) | 2015.2 |
| v4.0(Rev. 7) | 2015.1 |
| v4.0(Rev. 6) | 2014.4 |
| v4.0(Rev. 5) | 2014.3 |
| v4.0(Rev. 4) | 2014.2 |
| v4.0(Rev. 4) | 2014.1 |
| v4.0(Rev. 3) | 2013.4 |
| v4.0(Rev. 2) | 2013.3 |
| v4.0(Rev. 1) | 2013.2 |
| v4.0 | 2013.1 |
General Guidance
The table below provides answer records for general guidance when using the LogiCORE IP Discrete Fourier Transform (DFT) core.
| Answer Record | Title |
|---|---|
| N/A | N/A |
Known and Resolved Issues
The following table provides known issues for the LogiCORE IP Discrete Fourier Transform (DFT) core, starting with v4.0, initially released in Vivado 2013.1.
Note: The "Version Found" column lists the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
| Answer Record | Title | Version Found | Version Resolved: |
|---|---|---|---|
| (Xilinx Answer 70698) | Discrete Fourier Transform (DFT) v4.0 - Some configurations of the DFT IP core might be logically incorrect following synthesis when Vivado 2018.1 is used and synchronous reset is not present. This will manifest as mismatches versus behavioral simulation on all core outputs. | v4.0(Rev.15) | v4.0(Rev.15) |
| (Xilinx Answer 57570) | Discrete Fourier Transform (DFT) v4.0 (Rev. 2) - When behavioral simulation is run on the DFT v4.0 IP core with Cadence IES in 2013.3, some outputs do not agree with the C model output | v4.0(Rev.2) | v4.0(Rev.2) |
Revision History
| AR# 54475 | |
|---|---|
| Date | 04/09/2018 |
| Status | Active |
| Type | Release Notes |
| Devices |
|
| Tools |
|
| IP |
|