Supported devices can be found in the following three locations:
For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado design tools.
This table correlates the core version to the first Vivado design tools release version in which it was included.
|Core Version||Vivado Tools Version|
The table below provides answer records for general guidance when using the LogiCORE IP DUC/DDC Compiler core.
Known and Resolved Issues
The following table provides known issues for the LogiCORE IP DUC/DDC Compiler core, starting with v3.0, initially released in Vivado 2013.1.
Note: The "Version Found" column lists the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
|Answer Record||Title||Version Found||Version Resolved|
|(Xilinx Answer 59798)||Behavioral simulation using Synopsys VCS simulator may give incorrect outputs||v3.0(Rev. 4)||N/A|
|(Xilinx Answer 58585)||The core may issue a critical warning during implementation: "CRITICAL WARNING: [Netlist 29-98] The DSP48E2 multiplier has increased from 25x18 to 27x18"||v3.0(Rev. 3)||N/A|
|(Xilinx Answer 56376)||Some configurations of the DUC/DDC Compiler v3.0 core do not simulate correctly when Vivado Simulator is used to perform behavioral simulation||v3.0||N/A|
|(Xilinx Answer 55108)||Vivado fails to upgrade DUC/DDC Compiler v2.0 from 14.2 PlanAhead to Vivado||v2.0||v3.0|