This answer record contains the Release Notes and Known Issues for the LogiCORE IP G.709 FEC Encoder/Decoder core and includes the following:
This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2013.1 and newer tool versions.
Please reference XTP025 - IP Release Notes Guide for past known issue logs and ISE support information.
LogiCORE IP G.709 FEC Encoder/Decoder core IP Page:
Supported Devices can be found in the following three locations:
For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado.
Table 1 correlates the core version to the first Vivado design tools release version in which it was included.
Table 1: Version
|Vivado Tools |
|v2.0 (Rev. 2)||2013.3|
|v2.0 (Rev. 1)||2013.2|
Table 2 provides answer records for general guidance when using the LogiCORE IP G.709 FEC Encoder/Decoder core.
Table 2: General Guidance
Known and Resolved Issues
The following table provides known issues for the LogiCORE IP G.709 FEC Encoder/Decoder core, starting with v6.0, initially released in Vivado 2013.1.
Note: The "Version Found" column lists the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
|(Xilinx Answer 64600)||A setup timing violation can occur if Encoder implementation is set to BALANCED or DSP BIAS||v2.1 (Rev. 5)||N/A|
|(Xilinx Answer 59744)||Behavioral simulation using Synopsys VCS simulator can give incorrect results||v2.1 (Rev. 1)||N/A|
|(Xilinx Answer 57929)||Why does the core output incorrect data with 2013.3 Vivado Simulator?||v2.0 (Rev. 2)||N/A|