This answer record contains the Release Notes and Known Issues for the LogiCORE IP 3GPP LTE UL Channel Decoder core and includes the following:
This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2013.1 and newer tool versions.
Please reference XTP025 - IP Release Notes Guide for past known issue logs and ISE support information.
LogiCORE IP 3GPP LTE UL Channel Decoder core IP Page:
http://www.xilinx.com/content/xilinx/en/products/intellectual-property/do-di-chdec-lte.html
For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado.
Version Table
This table correlates the core version to the first Vivado design tools release version in which it was included.
| Core Version | Vivado Tools Version |
|---|---|
| v4.0 (Rev. 5) | 2014.2 |
| v4.0 (Rev. 4) | 2014.1 |
| v4.0 (Rev. 3) | 2013.4 |
| v4.0 (Rev. 2) | 2013.3 |
| v4.0 (Rev. 1) | 2013.2 |
| v4.0 | 2013.1 |
General Guidance
The table below provides answer records for general guidance when using the LogiCORE IP 3GPP LTE UL Channel Decoder core.
| Answer Record | Title |
|---|---|
| N/A | N/A |
Known and Resolved Issues
The following table provides known issues for the LogiCORE IP 3GPP LTE UL Channel Decoder core, starting with v4.0, initially released in Vivado 2013.1.
Note: The "Version Found" column lists the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
| Answer Record | Title | Version Found | Version Resolved |
|---|---|---|---|
| (Xilinx Answer 58760) | The event_irictrl_waiting output may be seen to behave incorrectly when simulating with VCS | V4.0(Rev. 3) | N/A |
| (Xilinx Answer 58588) | Some configurations of core fail to meet 100MHz when >250MHz is expected | v4.0(Rev. 3) | N/A |
| (Xilinx Answer 58586) | The core generated in Vivado 2013.4 does not deliver demo_tb/wave_<component_name>.do file which is described in the product guide | v4.0(Rev.2) | N/A |
| (Xilinx Answer 57928) | Why does the core output incorrect data with Cadence IES 12.20.016? | v4.0 (Rev. 2) | N/A |
| (Xilinx Answer 53465) | Why does my DSP Digital Communications core fail to simulate with error Error: Failed to find design work <Core name>? | v3.0 | v4.0 |
| (Xilinx Answer 52955) | Does this core support simultaneous soft and hard decode? | v3.0 | N/A |
| (Xilinx Answer 43783) | Does the C-Model User Guide (UG 807) have incorrect library references? | v3.0 | N/A |
Revision History
04/20/2014 - Added v4.0(Rev. 4) and v4.0(Rev. 5) to Version Table and (Xilinx Answer 60729)
12/12/2013 - Added (Xilinx Answer 58760)
11/29/2013 - Added (Xilinx Answer 58588)
11/29/2013 - Added (Xilinx Answer 58586)
10/11/2013 - Added (Xilinx Answer 57928)
04/03/2013 - Initial Release
| AR# 54484 | |
|---|---|
| Date | 11/10/2014 |
| Status | Active |
| Type | Release Notes |
| Tools | |
| IP | |