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AR# 54502

IP Release Notes and Known Issues for LogiCORE IP FIR Compiler core for Vivado 2013.1 and newer tools

Description

This answer record contains the Release Notes and Known Issues for the LogiCORE IP FIR Compiler core and includes the following:

  • General Information
  • Known and Resolved Issues
  • Revision History

This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2013.1 and newer tools.

Please reference XTP025 - IP Release Notes Guide for past known issue logs and ISE support information.

LogiCORE IP FIR Compiler core IP Page:

http://www.xilinx.com/content/xilinx/en/products/intellectual-property/fir_compiler.html

Solution

General Information

Supported Devices can be found in the following three locations:

For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado design tools.

Version Table

This table correlates the core version to the first Vivado design tools release version in which it was included.

Core VersionVivado Tools Version
v7.2(Rev. 7)2016.3
v7.2(Rev. 6)2016.2
v7.2(Rev. 6)2016.1
v7.2(Rev. 5)2015.4
v7.2(Rev. 4)2015.3
v7.2(Rev. 3)2015.2.1
v7.2(Rev. 3)2015.2
v7.2(Rev. 2)2015.1
v7.2(Rev. 1)2014.4.1
v7.2(Rev. 1)2014.4
v7.22014.3
v7.1(Rev. 4)2014.2
v7.1(Rev. 3)2014.1
v7.1(Rev. 2)2013.4
v7.1(Rev. 1)2013.3
v7.12013.2
v7.02013.1


General Guidance

The table below provides Answer Records for general guidance when using the LogiCORE IP FIR Compiler core.

Answer RecordTitle
N/A



Known and Resolved Issues

The following table provides known issues for the LogiCORE IP FIR Compiler core, starting with v7.0, initially released in Vivado Design Suite 2013.1.

Note: The "Version Found" column lists the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Answer RecordTitleVersion FoundVersion Resolved
(Xilinx Answer 55242)LogiCORE IP FIR Compiler v7.0 - Post-synthesis and post-implementation netlist output mismatches behavioral simulation output v7.0v7.1
(Xilinx Answer 55243)LogiCORE IP FIR Compiler v7.0 - Core is incorrectly synthesized when the core is configured with dynamic shift ram inference v7.0v7.1
(Xilinx Answer 57004)FIR Compiler v7.1 - Post-synthesis and post-implementation netlists issue BRAM memory collision errors during simulationv7.1v7.1 rev1
(Xilinx Answer 56225)2013.2 fir_compiler_v7_1 - Post-synthesis and post-implementation netlist output mismatches behavioral simulation output v7.1v7.1 rev1


Linked Answer Records

Child Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
29138 LogiCORE IP Finite Impulse Response Compiler (FIR Compiler) - Release Notes and Known Issues N/A N/A
AR# 54502
Date Created 02/24/2013
Last Updated 10/13/2016
Status Active
Type Release Notes
Tools
  • Vivado Design Suite - 2013.1
IP
  • FIR Compiler