This answer record contains the Release Notes and Known Issues for the LogiCORE IP FIR Compiler core and includes the following:
This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2013.1 and newer tools.
Please reference XTP025 - IP Release Notes Guide for past known issue logs and ISE support information.
LogiCORE IP FIR Compiler core IP Page:
Supported Devices can be found in the following three locations:
For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado design tools.
This table correlates the core version to the first Vivado design tools release version in which it was included.
|Core Version||Vivado Tools Version|
The table below provides Answer Records for general guidance when using the LogiCORE IP FIR Compiler core.
Known and Resolved Issues
The following table provides known issues for the LogiCORE IP FIR Compiler core, starting with v7.0, initially released in Vivado Design Suite 2013.1.
Note: The "Version Found" column lists the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
|Answer Record||Title||Version Found||Version Resolved|
|(Xilinx Answer 55242)||LogiCORE IP FIR Compiler v7.0 - Post-synthesis and post-implementation netlist output mismatches behavioral simulation output||v7.0||v7.1|
|(Xilinx Answer 55243)||LogiCORE IP FIR Compiler v7.0 - Core is incorrectly synthesized when the core is configured with dynamic shift ram inference||v7.0||v7.1|
|(Xilinx Answer 57004)||FIR Compiler v7.1 - Post-synthesis and post-implementation netlists issue BRAM memory collision errors during simulation||v7.1||v7.1 rev1|
|(Xilinx Answer 56225)||2013.2 fir_compiler_v7_1 - Post-synthesis and post-implementation netlist output mismatches behavioral simulation output||v7.1||v7.1 rev1|