This answer record contains the Release Notes and Known Issues for the LogiCORE IP RAM Based Shift Register core and includes the following:
This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2013.1 and forward.Please reference XTP025 - IP Release Notes Guide for past known issue logs and ISE support information.
LogiCORE IP RAM Based Shift Register core IP Page:
Supported Devices can be found in the following three locations:
For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado.
This table correlates the core version to the first Vivado design tools release version in which it was included.
|Core Version||Vivado Tools Version|
|12.0 (Rev. 10)||2016.3|
|12.0 (Rev. 9)||2016.2|
|12.0 (Rev. 9)||2016.1|
|12.0 (Rev. 8)||2015.4|
|12.0 (Rev. 7)||2015.3|
|12.0 (Rev. 6)||2015.2.1|
|12.0 (Rev. 6)||2015.2|
|12.0 (Rev. 6)||2015.1|
|12.0 (Rev. 5)||2014.4|
|12.0 (Rev. 4)||2014.3|
|12.0 (Rev. 4)||2014.2|
|12.0 (Rev. 4)||2014.1|
|12.0 (Rev. 3)||2013.4|
|12.0 (Rev. 2)||2013.3|
|12.0 (Rev. 1)||2013.2|
The table below provides Answer Records for general guidance when using the LogiCORE IP RAM Based Shift Register core.
|Article Number||Article Title|
Known and Resolved Issues
The following table provides known issues for the LogiCORE IP RAM Based Shift Register core, starting with v12.0, initially released in Vivado 2013.1.
Note: The "Version Found" column lists the version the problem was first discovered.
The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
|Answer Record||Title||Version Found||Version Resolved|