This answer record contains the Release Notes and Known Issues for the LogiCORE IP Asynchronous Sample Rate Converter (ASRC) core and includes the following:
This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2013.1 and newer tool versions.
For past known issue logs and ISE support information, see the IP Release Notes Guide (XTP025):
NOTE: Not recommended for new designs. The core is removed from the IP catalog as of 2014.3
Supported devices can be found in the following location:
For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado.
Table 1 correlates the core version to the first Vivado design tools release version in which it was included.
Table 1: Version
|Vivado Tools |
|v2.0 (Rev. 3)||2014.1|
|v2.0 (Rev. 2)||2013.3|
|v2.0 (Rev. 1)||2013.2|
Table 2 provides answer records for general guidance when using the LogiCORE IP Asynchronous Sample Rate Converter (ASRC) core.
Table 2: General Guidance
|(Xilinx Answer 50170)||Why do I see variation or "glitches" on the output when my input is a DC value?|
|(Xilinx Answer 52645)||Does clock jitter affect the ASRC results and can it cause THD glitches?|
|(Xilinx Answer 52889)||Why do I see jitter when the input and output are the same sample rate using the automatic mode, but not for manual mode?|
Known and Resolved Issues
The following table provides known issues for the LogiCORE IP Asynchronous Sample Rate Converter (ASRC) core, starting with v2.0, initially released in Vivado Design Suite 2013.1.
Note: The "Version Found" column lists the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
|Answer Record||Title||Version |