For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado design tools.
This table correlates the core version to the first Vivado design tools release version in which it was included.
|v6.0 (Rev. 2)||2013.3|
|v6.0 (Rev. 1)||2013.2|
The table below provides answer records for general guidance when using the LogiCORE IP Color Correction Matrix core.
Known and Resolved Issues
The following table provides known issues for the LogiCORE IP Color Correction Matrix core, starting with v6.0, initially released in Vivado 2013.1.
Note: The "Version Found" column lists the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
|Answer Record||Title||Version Found||Version Resolved|
|(Xilinx Answer 57773)||Why does the TREADY stall when using the TEST_PATTERN or BYPASS options available in some of the Video IP when the Include Debug Features option is enabled at generation?||v5.01.a||N/A|
|(Xilinx Answer 52215)||Why does my core fail timing with a Critical Warning?||v5.01.a||v6.0 (Rev. 2)|
|(Xilinx Answer 56274)||Vivado 2013.2 Multimedia Video and Imaging - How do I properly constrain the Video IP in my design?||v6.0||v6.0 (Rev. 2)|
|(Xilinx Answer 55980)||Why do I see write failures on the AXI4-Lite bus, when the AXI4-Stream clock is at a different frequency than the AXI4-Lite interface clock?||v6.0||v6.0 (Rev. 1)|