This answer record contains the Release Notes and Known Issues for the LogiCORE IP Defective Pixel Correction core and includes the following:
This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2013.1 and newer tool versions.
Please reference XTP025 - IP Release Notes Guide for past known issue logs and ISE support information.
LogiCORE IP Defective Pixel Correction core IP Page:
Supported devices can be found in the following locations:
For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado design tools.
This table correlates the core version to the first Vivado design tools release version in which it was included.
|Vivado Tools |
|v7.0 (Rev. 3)||2013.4|
|v7.0 (Rev. 2)||2013.3|
|v7.0 (Rev. 1)||2013.2|
The table below provides answer records for general guidance when using the LogiCORE IP Defective Pixel Correction core.
Known and Resolved Issues
The following table provides known issues for the LogiCORE IP Defective Pixel Correction core, starting with v7.0, initially released in Vivado 2013.1.
Note: The "Version Found" column lists the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
|Answer Record||Title||Version Found||Version Resolved|
|(Xilinx Answer 59494)||No video passes through when debug features are enabled||v7.0||N/A|
|(Xilinx Answer 58423)||Why do I get a rresp=0x2 slave error, when trying to read register address 0x120?||v6.01.a||v6.01.a|
|(Xilinx Answer 57773)||Why does the TREADY stall when using the TEST_PATTERN or BYPASS options available in some of the Video IP when the Include Debug Features option is enabled at generation?||v6.01.a||N/A|
|(Xilinx Answer 52215)||Why does my core fail timing with a Critical Warning?||v6.01.a||v7.0 (Rev. 2)|
|(Xilinx Answer 56274)||Vivado 2013.2 Multimedia Video and Imaging - How do I properly constrain the Video IP in my design?||v7.0||v7.0 (Rev. 2)|
|(Xilinx Answer 55980)||Why do I see write failures on the AXI4-Lite bus, when the AXI4-Stream clock is at a different frequency than the AXI4-Lite interface clock?||v7.0||v7.0 (Rev. 1)|