This answer record contains the Release Notes and Known Issues for the Image Enhancement LogiCORE IP and includes the following:
This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2013.1 and newer tool versions.
Please reference XTP025 - IP Release Notes Guide for past known issue logs and ISE support information.
Image Enhancement LogiCORE IP Page:
Note: This core was formerly called the Image Edge Enhancement core.
Obsoleted in Vivado 2019.1 and not recommended for new designs.
See the IP page to search available Xilinx and third party partner IP.
Supported devices can be found in the following three locations:
For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado design tools.
This table correlates the core version to the first Vivado design tools release version in which it was included.
|Vivado Tools |
|v8.0 (Rev. 15)||2018.3||(Xilinx Answer 71806)|
|v8.0 (Rev. 14)||2017.4||(Xilinx Answer 70386)|
|v8.0 (Rev. 13)||2017.3|
|v8.0 (Rev. 12)||2016.4|
|v8.0 (Rev. 11)|
|v8.0 (Rev. 10)|
|v8.0 (Rev. 9)|
|v8.0 (Rev. 8)|
|v8.0 (Rev. 7)|
|v8.0 (Rev. 6)|
|v8.0 (Rev. 5)|
|v8.0 (Rev. 4)|
|v8.0 (Rev. 3)||2014.1|
|v8.0 (Rev. 2)||2013.4|
|v8.0 (Rev. 1)||2013.3|
The table below provides answer records for general guidance when using the Image Enhancement LoGiCORE IP.
Known and Resolved Issues
The following table provides known issues for the LogiCORE IP Image Enhancement core, starting with v7.0, initially released in Vivado 2013.1.
Note: The "Version Found" column lists the version the problem was first discovered.
The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
|Answer Record||Title||Version Found||Version Resolved|
|(Xilinx Answer 61998)||What values are legal for various core parameters?||v8.0||N/A|
|(Xilinx Answer 60173)||Why does the Image Enhancement core output data in the wrong columns after changing the number of columns via the AXI4-Lite interface?||v8.0||N/A|
|(Xilinx Answer 57773)||Why does the TREADY stall when using the TEST_PATTERN or BYPASS options available in some of the Video IP when the Include Debug Features option is enabled at generation?||v5.01.a||v8.0 (Rev. 3)|
|(Xilinx Answer 52215)||Why does my core fail timing with a Critical Warning?||v5.01.a||v8.0 (Rev. 1)|
|(Xilinx Answer 56274)||Vivado 2013.2 Multimedia Video and Imaging - How do I properly constrain the Video IP in my design?||v7.0||v8.0 (Rev. 1)|
|(Xilinx Answer 55980)||Why do I see write failures on the AXI4-Lite bus, when the AXI4-Stream clock is at a different frequency than the AXI4-Lite interface clock?||v7.0||v7.0 (Rev. 1)|
Please seek technical support via the Video Board. The Xilinx Forums are a great resource for technical support.
The entire Xilinx User Community is available to help here, and you can ask questions and collaborate with Xilinx experts to get the solutions you need.
|01/04/2019||Added v8.0 (Rev. 4 -15) added obsolete link and forum link|
|09/10/2014||Added (Xilinx Answer 61998).|
|10/23/2013||Added v8.0 (Rev. 1) to Version Table, (Xilinx Answer 57773) and updated Known and Resolved Issues table for 2013.3.|
|06/19/2013||Added v8.0 to Version Table, (Xilinx Answer 56274), (Xilinx Answer 55980)|