This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2013.1 and forward.
Please reference XTP025 - IP Release Notes Guide for past known issue logs and ISE support information.
LogiCORE IP Object Segmentation core IP Page:
http://www.xilinx.com/content/xilinx/en/products/intellectual-property/ef-di-vid-obj-seg.html
Note: Not recommended for new designs. The core is removed from IP catalog as of 2014.1. Please contact Xylon, our IP partner, for solutions related to object segmentation.
Core Version | Vivado Tools Version |
---|---|
v3.00.a | 2013.1 |
Article Number | Article Title |
---|---|
N/A | N/A |
Article Number | Article Title | Version Found | Version Resolved |
---|---|---|---|
(Xilinx Answer 56274) | Vivado 2013.2 Multimedia Video and Imaging - How do I properly constrain the Video IP in my design? | v3.00.a | N/A |
Answer Number | Answer Title | Version Found | Version Resolved |
---|---|---|---|
56852 | Xilinx Multimedia, Video and Imaging Solution Center - Top Issues | N/A | N/A |
Answer Number | Answer Title | Version Found | Version Resolved |
---|---|---|---|
56274 | Vivado 2013.2 Multimedia Video and Imaging - How do I properly constrain the Video IP in my design? | N/A | N/A |
55980 | LogiCORE Video Timing Controller v5.01.a - Why do I see write failures on the AXI4-Lite bus, when the AXI4-Stream clock is at a different frequency than the AXI4-Lite interface clock? | N/A | N/A |
AR# 54529 | |
---|---|
Date | 11/11/2014 |
Status | Archive |
Type | Release Notes |
IP |