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  3. AR# 54529: LogiCORE IP Object Segmentation - Release Notes and Known Issues for Vivado 2013.1 and newer tool versions

AR# 54529

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LogiCORE IP Object Segmentation - Release Notes and Known Issues for Vivado 2013.1 and newer tool versions

Description

This answer record contains the Release Notes and Known Issues for the LogiCORE IP Object Segmentation core and includes the following:
  • General Information
  • Known and Resolved Issues
  • Revision History

This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2013.1 and forward.
Please reference XTP025 - IP Release Notes Guide for past known issue logs and ISE support information.

LogiCORE IP Object Segmentation core IP Page:
http://www.xilinx.com/content/xilinx/en/products/intellectual-property/ef-di-vid-obj-seg.html

Note: Not recommended for new designs. The core is removed from IP catalog as of 2014.1. Please contact Xylon, our IP partner, for solutions related to object segmentation.

Solution

General Information

Supported Devices can be found in the following three locations:
For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado design tools.

Version Table
This table correlates the core version to the first Vivado design tools release version in which it was included.
Core Version Vivado Tools Version
v3.00.a 2013.1

General Guidance
The table below provides Answer Records for general guidance when using the LogiCORE IP Object Segmentation core.
Article Number Article Title
N/A N/A


Known and Resolved Issues
The following table provides known issues for the LogiCORE IP Object Segmentation core, starting with v3.00.a, initially released in Vivado 2013.1.
Note: The "Version Found" column lists the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
Article Number Article Title Version Found Version Resolved
(Xilinx Answer 56274) Vivado 2013.2 Multimedia Video and Imaging - How do I properly constrain the Video IP in my design? v3.00.a N/A


Revision History:
04/16/2014 - Note: Not recommended for new designs. The core is removed from IP catalog as of 2014.1. Please contact Xylon, our IP partner, for solutions related to object segmentation.
06/16/2013 - Added (Xilinx Answer 56274), (Xilinx Answer 55980)
04/03/2013 - Initial Release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
56852 Xilinx Multimedia, Video and Imaging Solution Center - Top Issues N/A N/A

Child Answer Records

Answer Number Answer Title Version Found Version Resolved
56274 Vivado 2013.2 Multimedia Video and Imaging - How do I properly constrain the Video IP in my design? N/A N/A
55980 LogiCORE Video Timing Controller v5.01.a - Why do I see write failures on the AXI4-Lite bus, when the AXI4-Stream clock is at a different frequency than the AXI4-Lite interface clock? N/A N/A
AR# 54529
Date 11/11/2014
Status Archive
Type Release Notes
IP
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