AR# 54536
|LogiCORE IP Test Pattern Generator (TPG) - Release Notes and Known Issues for Vivado 2013.1 and newer tool versions
Description
This answer record contains the Release Notes and Known Issues for the Test Pattern Generator (TPG) LogiCORE IP and includes the following:
- General Information
- Known and Resolved Issues
- Revision History
This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2013.1 and newer tool versions.
Please reference XTP025 - IP Release Notes Guide for past known issue logs and ISE support information.
Test Pattern Generator LogiCORE IP Page:
https://www.xilinx.com/content/xilinx/en/products/intellectual-property/tpg.html
Solution
General Information
Supported devices can be found in the following three locations:
- Test Pattern Generator LogiCORE IP Product Guide
- Test Pattern Generator LogiCORE IP Page
- Open the Vivado tool -> IP Catalog, right-click on an IP and select Compatible Families.
For a list of new features and added device support for all versions:
- Subsystem or IP - See the Changelog included with the core in Vivado.
- Subsystem or IP - Click on the Changelog links below.
- Standalone Software Drivers - See the Changelog included with the Doxygen Drivers in Xilinx SDK
- Standalone Software Drivers - Github Software Driver Repo
- Linux Drivers - Xilinx Wiki
Please seek technical support via the Video Board of the Xilinx Community Forums.
The Xilinx Forums are a great resource for technical support.
The entire Xilinx User Community is available to help here, and you can ask questions and collaborate with Xilinx experts to get the solutions you need.
Version Table
This table correlates the core version to the first Vivado design tools release version in which it was included.
| Core Version | Vivado Tools Version | IP Changelog |
|---|---|---|
| 8.0 | 2018.3 | (Xilinx Answer 71806) |
| 7.0 (Rev. 11) | 2018.2 | (Xilinx Answer 71212) |
| 7.0 (Rev. 10) | 2018.1 | (Xilinx Answer 70699) |
| v7.0 (Rev. 9) | 2017.4 | (Xilinx Answer 70386) |
| v7.0 (Rev. 8) | 2017.3 | (Xilinx Answer 69903) |
| v7.0 (Rev. 7) | 2017.2 | (Xilinx Answer 69326) |
| v7.0 (Rev. 6) | 2017.1 | (Xilinx Answer 69055) |
| v7.0 (Rev. 5) | 2016.4 | (Xilinx Answer 68369) |
| v7.0 (Rev. 4) | 2016.3 | (Xilinx Answer 68021) |
| v7.0 (Rev. 3) | 2016.2 | (Xilinx Answer 67345) |
| v7.0 (Rev. 2) | 2016.1 | (Xilinx Answer 66930) |
| v7.0 (Rev. 1) | 2015.4 | (Xilinx Answer 66004) |
| v7.0 | 2015.3 | (Xilinx Answer 65570) |
| v6.0 (Rev. 4) | 2015.1 | N/A |
| v6.0 (Rev. 3) | 2014.4 | (Xilinx Answer 62882) |
| v6.0 (Rev. 2) | 2014.3 | (Xilinx Answer 62144) |
| v6.0 (Rev. 1) | 2014.2 | N/A |
| v6.0 | 2014.1 | (Xilinx Answer 59986) |
| v5.0 (Rev. 3) | 2013.4 | N/A |
| v5.0 (Rev. 2) | 2013.3 | N/A |
| v5.0 (Rev. 1) | 2013.2 | N/A |
| v5.0 | 2013.1 | N/A |
General Guidance
The table below provides answer records for general guidance when using the LogiCORE IP Test Pattern Generator core.
| Answer Record | Title |
|---|---|
| (Xilinx Answer 71759) | Why do I get the error "ERROR: [HLS 200-101] 'add_files': Too many positional arguments specified." when using HLS Based Video IPs |
| (Xilinx Answer 68009) | Upgrade from 2016.2 to 2016.3 changes the behavior of the Test Pattern Generator |
| (Xilinx Answer 66350) | IP is locked due to licensing error after migration from v6.0 |
| (Xilinx Answer 65707) | Constant mode no longer available |
Known and Resolved Issues
The following table provides known issues for the LogiCORE IP Test Pattern Generator core, starting with v5.0, initially released in the Vivado 2013.1 tool.
Note: The "Version Found" column lists the version the problem was first discovered.
The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
| Answer Record | Title | Version Found | Version Resolved |
|---|---|---|---|
| (Xilinx Answer 70421) | Why do I see synthesis failures when using a Windows OS for synthesis? | v7.0 (Rev. 8) | N/A |
| (Xilinx Answer 67206) | Why does the Test Pattern Generator fail to meet timing when used in 2 pixel per clock interface mode? | v7.0 | N/A |
| (Xilinx Answer 68086) | Maximum S_AXI "Tdata_num_bytes" Data Width Incorrectly Set | V7.0 | N/A |
| (Xilinx Answer 65784) | Error-[XMRE] Cross-module reference resolution error | v7.0 | N/A |
| (Xilinx Answer 65783) | [filemgmt 20-1741] File 'v_tpg_config.h' is used by one or more modules | v7.0 | v7.0 (Rev. 1) |
| (Xilinx Answer 63688) | Slice range direction "to" does not match prefix slice direction "downto" | v6.0 (Rev 1) | v7.0 |
| (Xilinx Answer 60167) | Why does the Test Pattern Generator stop working after ~3-4 hours? | v5.0 (Rev. 3) | v6.0 |
| (Xilinx Answer 59271) | Why is the output corrupt when the Test Pattern Generator (TPG) is configured for YUV 4:4:4 and bypass mode is selected? | v4.00.a | v6.0 |
| (Xilinx Answer 56274) | Vivado 2013.2 Multimedia Video and Imaging - How do I properly constrain the Video IP in my design? | v5.0 | v5.0 (Rev. 2) |
| (Xilinx Answer 54660) | When using the Video Timing Controller, Test Pattern Generator, RGB2YCrCb Color-Space Converter or YCrCb2RGB Color-Space Converter cores, why do I get an error saying that my design can not generate a bitstream? | v4.01.a | v5.0 (Rev. 2) |
| (Xilinx Answer 55980) | Why do I see write failures on the AXI4-Lite bus, when the AXI4-Stream clock is at a different frequency than the AXI4-Lite interface clock? | v5.0 | v5.0 (Rev. 1) |
| (Xilinx Answer 56929) | Color bars are incorrect colors in constant RGB mode | v5.0 | v5.0 (Rev. 1) |
| Revision History | |
|---|---|
| 01/04/2019 | Added v8.0 to Version Table. |
| 11/28/2018 | Added v7.0 (Rev. 10), v7.0 (Rev. 11) and v8.0 to Version Table. Added |
| 01/17/2018 | Added v7.0 (Rev. 6), v7.0 (Rev. 7), v7.0 (Rev. 8) and v7.0 (Rev. 9) to Version Table. Added (Xilinx Answer 70421) |
| 01/31/2017 | Added v7.0 (Rev. 5) to Version Table. Added (Xilinx Answer 67206) |
| 10/17/2016 | Added (Xilinx Answer 68086) to known issues |
| 10/05/2016 | Added v7.0 (Rev. 3) and v7.0 (Rev. 4) to Version Table. Added (Xilinx Answer 68009) |
| 04/06/2016 | Added v7.0 (Rev. 1) and v7.0 (Rev. 2) to Version Table. |
| 01/07/2016 | Added (Xilinx Answer 66350) |
| 10/28/2015 | Added v7.0 to Version Table, added (Xilinx Answer 65783), (Xilinx Answer 65784) |
| 03/13/2015 | Added (Xilinx Answer 63688) |
| 08/18/2014 | Added (Xilinx Answer 54536) |
| 04/16/2014 | Added v6.0 to Version Table and (Xilinx Answer 60167) updated Known and Resolved Issues table for 2014.1 |
| 01/29/2014 | Added v5.0 (Rev. 3) to Version Table and (Xilinx Answer 59271) |
| 10/23/2013 | Added v5.0 (Rev. 2) to Version Table, (Xilinx Answer 54660) and updated Known and Resolved Issues table for 2013.3 |
| 06/19/2013 | Added v5.0 (Rev. 1) to Version Table, (Xilinx Answer 56274), (Xilinx Answer 55980) |
| 04/03/2013 | Initial release |
Linked Answer Records
Master Answer Records
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 56852 | Xilinx Multimedia, Video and Imaging Solution Center - Top Issues | N/A | N/A |
Child Answer Records
Associated Answer Records
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 61625 | Video IP Example Design Landing Page | N/A | N/A |
| AR# 54536 | |
|---|---|
| Date | 01/22/2019 |
| Status | Active |
| Type | Release Notes |
| Tools | |
| IP | |