This answer record contains the Release Notes and Known Issues for the Serial I/O Debug Cores and includes the following:
This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2013.1 and newer tool versions.
This answer record covers all Vivado Serial I/O Debug Cores.
For a list of new features and added device support for all versions, see the Change Log file available with the core in the Vivado tool.
Known and Resolved Issues
The following table provides known issues for the Vivado Serial IO Debug
Note: The "Version Found" column lists the version the problem was first discovered.
The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
|Answer Record||Title||Version Found|
|(Xilinx Answer 69206)||IBERT - RXOUTCLK frequency gets doubled when using IN-System IBERT core||2017.1|
|(Xilinx Answer 68998)||UltraScale/UltraScale+ Reference Clock propagation delay problem - IBERT detection issue, and CPLL lock issue||2017.1|
|(Xilinx Answer 67029)||Using a transceiver reference clock as the system clock for a debug core such as IBERT||All|
|(Xilinx Answer 67536)||IBERT - How to use Tcl to display the BER/error count||All|
|(Xilinx Answer 68131)||IBERT GTH 2016.1 Unable to set PORT.GTTXRESET = 1||2016.1|
|(Xilinx Answer 68675)||How do I use the UltraScale+ GTY FPLL with IBERT||All|
9/8/2017 - updated to 2017.1