You are using a deprecated Browser. Internet Explorer is no longer supported by Xilinx.
2013.x Vivado-Timing - report_clocks generate duplicate clocks in the report
When I execute the Tcl command report_clocks, the tool reports duplicate clocks.
For example, the derived constraint on pll output (pll0) is reported twice as:
In reality, the signal CLK_OUT1_my_pll0_1 does not exist.
Also I do not see this constraint in the timing analysis.
What is the reason behind this?
This is a reporting error which is scheduled to be fixed in the next major release.
Until then, you can safely ignore this error.
Was this Answer Record helpful?