When I execute the Tcl command report_clocks, the tool reports duplicate clocks.
For example, the derived constraint on pll output (pll0) is reported twice as:
In reality, the signal CLK_OUT1_my_pll0_1 does not exist.
Also I do not see this constraint in the timing analysis.
What is the reason behind this?
AR# 54627 | |
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Date | 08/26/2014 |
Status | Active |
Type | General Article |
Tools |