2. Support
  3. AR# 54627: 2013.x Vivado-Timing - report_clocks generate duplicate clocks in the report

AR# 54627

2013.x Vivado-Timing - report_clocks generate duplicate clocks in the report

Description

When I execute the Tcl command report_clocks, the tool reports duplicate clocks.

For example, the derived constraint on pll output (pll0) is reported twice as:


  1. CLK_OUT1_my_pll0
  2. CLK_OUT1_my_pll0_1
     



In reality, the signal CLK_OUT1_my_pll0_1 does not exist.

Also I do not see this constraint in the timing analysis.

What is the reason behind this?

Solution

This is a reporting error which is scheduled to be fixed in the next major release.

Until then, you can safely ignore this error.
AR# 54627
Date 08/26/2014
Status Active
Type General Article
Tools