This answer record contains the Release Notes and Known Issues for the Soft Error Mitigation Core and includes the following:
This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2013.1 and newer tools.
Please reference XTP025 - IP Release Notes Guide for past known issue logs and ISE support information.
This release notes does not include Virtex-6, or Spartan-6 because these devices are supported in ISE tool only.
For the release notes of SEM IP targeting UltraScale devices, please reference (Xilinx Answer 63609) UltraScale Soft Error Mitigation Controller - Release Notes
LogiCORE Soft Error Mitigation Core IP Page:
http://www.xilinx.com/content/xilinx/en/products/intellectual-property/sem.html
General Information
Supported Devices can be found in the following three locations:
For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado design tools.
Version Table
This table correlates the core version to the first Vivado design tools release version in which it was included.
| Core Version | Vivado Tools Version |
|---|---|
| v4.0.0 | 2013.1 |
| v4.0.1 | 2013.2 |
| v4.0.2 | 2013.3 |
| v4.1.0 | 2014.1 |
| v4.1.1 | 2014.2 |
| v4.1.2 | 2014.3 |
| v4.1.3 | 2014.4 |
| v4.1.4 | 2015.1 |
| v4.1.5 | 2015.3 |
| v4.1.6 | 2016.2 |
| v4.1.7 | 2016.3 |
| v4.1.8 | 2017.1 |
Supported Devices
For all 7 Series FPGA and Zynq-7000 SoC devices supported prior to 2016, SEM IP is a Production IP. For all newer devices, the IP status is described below:
Device | IP Status | Remark |
XC7A12T | Pre-Production | Hardware Validation Pending |
XC7A25T | Pre-Production | Hardware Validation Pending |
XC7Z007S | Pre-Production | This IP is Production ready. The Pre-Production label in Vivado 2017.1 is incorrect. |
XC7Z012S | Pre-Production | This IP is Production ready. The Pre-Production label in Vivado 2017.1 is incorrect. |
XC7Z014S | Pre-Production | This IP is Production ready. The Pre-Production label in Vivado 2017.1 is incorrect. |
XC7S6 | Pre-Production | Hardware Validation Pending |
XC7S15 | Pre-Production | Hardware Validation Pending |
XC7S25 | Pre-Production | Hardware Validation Pending |
XC7S50 | Pre-Production | Hardware Validation Pending |
XC7S75 | Pre-Production | Hardware Validation Pending |
XC7S100 | Pre-Production | Hardware Validation Pending |
General Guidance
The table below provides answer records for general guidance when using the LogiCORE IP Soft Error Mitigation core.
| Answer Record | Title |
|---|---|
| (Xilinx Answer 42103) | Soft Error Mitigation Controller - Frequently Asked Questions |
| (Xilinx Answer 54460) | How to use SEM v4.0 with Vivado Lab Tools 2013.1 |
| (Xilinx Answer 47291) | Soft Error Mitigation Controller - Example Design XDC Pin out Constraints for the VC707 and KC705 Boards |
| (Xilinx Answer 51043) | Soft Error Mitigation (SEM) IP - SEM IP Core fails to initialize when configuration is done through Digilent programming solution |
| (Xilinx Answer 58045) | Soft Error Mitigation Controller How do you optimally set the pblock size? |
| (Xilinx Answer 58046) | Soft Error Mitigation Controller - (PG036) Updates for v4.0 rev 2 Release |
| (Xilinx Answer 57409) | Virtex-7 SSIT devices ICAP access limitation |
| (Xilinx Answer 62337) | Soft Error Mitigation 7 Series and Zynq-7000 Support for Bitstream Encryption and Authentication |
| (Xilinx Answer 62338) | Soft Error Mitigation Recommendation on use of BUFGCE for clocking SEM IP |
| (Xilinx Answer 65402) | Soft Error Mitigation (SEM) IP - When performing error injection into configuration memory high performance interfaces may experience bit errors. |
| (Xilinx Answer 66975) | Zynq 7000 - Switching between ICAP and PCAP Recommendations |
| (Xilinx Answer 67180) | Can SEM support clock frequencies lower than 8 MHz? |
| (Xilinx Answer 61241) | Soft Error Mitigation IP Guidance for testing with error injection |
| (Xilinx Answer 65539) | Soft Error Mitigation IP - What is the valid range of addresses for error injection by LFA targeting Virtex-6, 7 Series, and Zynq-7000 devices? |
| (Xilinx Answer 67337) | 7 Series - SEM IP - How to use the SEM IP error report to look up bit error locations using essential bit data in an EBD file |
Known and Resolved Issues
The following table provides known issues for the Soft Error Mitigation core, starting with v4.0, initially released in Vivado 2013.1.
For previous version Known Issues, see (Xilinx Answer 44541).
Note: The "Version Found" column lists the version the problem was first discovered.
The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
| Answer Record | Title | Version Found | Version Resolved |
|---|---|---|---|
| (Xilinx Answer 67939) | Soft Error Mitigation IP - Location of the makedata.tcl file changed since 2016.3 | 2016.3 | no Fix |
| (Xilinx Answer 67055) | Vivado 2016.1 - 7 Series / Zynq-7000 - Soft Error Mitigation IP generation issue | 2016.1 | 2016.2 |
| (Xilinx Answer 47338) | Soft Error Mitigation Controller - Vivado 2012.2 Place Error when using pblock constraints on Virtex-7 and Kintex-7 devices | v3.2 | v4.0 rev2 |
| (Xilinx Answer 56151) | iMPACT, 7 series - When configuring SSIT devices, StartupClk must be set to JtagClk to avoid delay between the startup of SLRs | v3.4 | v4.0 rev2 |
| (Xilinx Answer 55299) | v4.0 - Setup time violations on Artix-7 and Zynq-7000 devices with 100 MHz ICAP clock | v4.0 rev0 | No Fix |
| (Xilinx Answer 55673) | 2013.1 write_bitstream - Bitstream masking issue affecting Readback CRC and SEM IP in designs using Virtex-7 FPGA GTH Article | v 4.0 rev0 | Vivado 2013.2 Non SSI Vivado 2013.3 SSI only |
| (Xilinx Answer 55370) | Soft Error Mitigation - V3.5 targeting SSI Device Article | v 4.0 rev0 | v4.0 rev1 |
| (Xilinx Answer 58044) | Soft Error Mitigation Controller XC7Z015 placer error when using correction by enhanced repair | 2013.3 | 2013.4 |
| (Xilinx Answer 58043) | Soft Error Mitigation Controller Setup time violation if using SEM v4.0 rev 2 IP with error injection shim set to ChipScope | v4.0 rev2 | v4.1.0 |
| (Xilinx Answer 59793) | Vivado 2013.4 - SEM_IP v 4.0 - No makedata.tcl file created | 2013.4 | 2014.1 |
| (Xilinx Answer 60055) | IP Soft Error Mitigation Timing warning for the VIO core | 2014.1 | N/A |
| (Xilinx Answer 60056) | IP Soft Error Mitigation makedata.tcl file listed in simulation source in Vivado tool | 2014.1 | 2014.2 |
| (Xilinx Answer 60058) | IP Soft Error Mitigation v4.1 Production support parts | 2014.1 | 2014.2 |
| (Xilinx Answer 60059) | IP Soft Error Mitigation Example Design exceeds physical I/O count of xc7z010 | v4.1.0 | No Fix |
| (Xilinx Answer 62087) | IP Soft Error Mitigation 7 series status_heartbeat specification | 2013.1 | 2014.4 |
| (Xilinx Answer 65308) | Soft Error Mitigation IP - 7 Series and Zynq-7000 Enhanced Repair initialization times are incorrect in (PG036) for select devices. (PG036) will be updated with the correct numbers in Vivado 2015.3. | 2013.1 | 2015.3 |
Revision History
| 04/03/2013 | Initial release |
| 06/03/2013 | Revised with new issues |
| 06/20/2013 | Revised for 2013.2 |
| 10/28/2013 | Revised for 2013.3 |
| 4/7/2014 | Revised for 2014.1 |
| 10/3/2014 | Revised for 2014.3 |
10/08/2015 | Revised for 2015.3 |
| 3/24/2017 | Revised for 2017.1 |
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 54733 | Soft Error Mitigation Controller - Release Notes and Known Issues for ISE Versions 14.5 and later tools | N/A | N/A |