This answer record contains the Release Notes and Known Issues for the 32/64-bit Initiator/Target for PCI (7 series) Core and includes the following:
This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2013.1 and newer tool versions.
Please reference XTP025 - IP Release Notes Guide for past known issue logs and ISE support information.
Xilinx PCI Express Cores Page:
Supported devices can be found in the following locations:
For a list of new features and added device support for all versions, see the Change Log file available with the core in the Vivado tool.
Changes in v5.0
This table correlates the core version to the first Vivado design tools release version in which it was included.
|Vivado Tools |
Known and Resolved Issues
The following table provides known issues for the 32-bit Initiator/Target for PCI (7 series) core, starting with v5.0, initially released in the Vivado 2013.1 tool.
Note: The "Version Found" column lists the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
|(Xilinx Answer 59580)||Artix7 35t, 50t and 75t devices support||v5.0||Not Resolved Yet|
|(Xilinx Answer 58163)||32-bit Initiator/Target for PCI v5.0 - Vivado Cannot Disable BAR||v5.0||Not Resolved Yet|