Description

This answer record contains the Release Notes and Known Issues for the 32/64-bit Initiator/Target for PCI (7 series) Core and includes the following:

• General Information
• Known and Resolved Issues
• Revision History
  

This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2013.1 and newer tool versions.
Please reference XTP025 - IP Release Notes Guide for past known issue logs and ISE support information.

Xilinx PCI Express Cores Page:
http://www.xilinx.com/products/design_resources/conn_central/protocols/pci_pcix.htm

Solution

General Information

Supported devices can be found in the following locations:

• 32/64-bit Initiator/Target for PCI (7 series) Core Product Guide
• Open the Vivado tool -> IP Catalog, right-click on an IP and select "Compatible Families"

For a list of new features and added device support for all versions, see the Change Log file available with the core in the Vivado tool.

Changes in v5.0

• Kintex-7 marked as production
• Simulation scripts are removed from the core database
• Modified the description to correct the text
• Fixed CR 697944
• Updated tap delay to close timing for Zynq-7000 devices

Version Table

This table correlates the core version to the first Vivado design tools release version in which it was included.

Known and Resolved Issues

The following table provides known issues for the 32-bit Initiator/Target for PCI (7 series) core, starting with v5.0, initially released in the Vivado 2013.1 tool.

Note: The "Version Found" column lists the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History

03/07/2014 - Added (Xilinx Answer 59580)
10/28/2013 - Added (Xilinx Answer 58163)
04/03/2013 - Initial release