UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 54661

Vivado 2013.1 and Forward - IP Release Notes and Known Issues for Distributed Memory Generator

Description

This answer record contains the Release Notes and Known Issues for the Distributed Memory Generator and includes the following:

  • General Information
  • Known and Resolved Issues
  • Change Log History
  • Revision History

This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2013.1 and forward.
Please reference XTP025 - IP Release Notes Guide for past known issue logs and ISE support information.

For the latest core updates, see the product page at:
http://www.xilinx.com/content/xilinx/en/products/intellectual-property/dist_mem_gen.html

Solution

General Information

Supported devices can be found in the following three locations:

For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado.

Version Table
This table correlates the core version to the first Vivado design tools release version in which it was included.

Core VersionVivado Tools Version
v8.0(Rev. 11)2016.3
v8.0(Rev. 10)2016.2
v8.0(Rev. 10)2016.1
v8.0(Rev. 9)2015.4.2
v8.0(Rev. 9)2015.4.1
v8.0(Rev. 9)2015.4
v8.0(Rev. 9)2015.3
v8.0(Rev. 8)2015.2.1
v8.0(Rev. 8)2015.2
v8.0(Rev. 8)2015..1
v8.0(Rev. 7)2014.4.1
v8.0(Rev. 7)2014.4
v8.0(Rev. 6)2014.3
v8.0(Rev. 5)2014.2
v8.0(Rev. 4)2014.1
v8.0(Rev. 3)
2013.4
v8.0(Rev. 2)
2013.3
v8.0(Rev. 1)
2013.2
v8.02013.1

General Guidance

The table below provides answer records for general guidance when using the LogiCORE Distributed Memory Generator core.

Answer RecordTitle
N/A
 N/A

Known and Resolved Issues

The following table provides known issues for the LogiCORE Distributed Memory Generator core, starting with v8.0, initially released in Vivado 2013.1.

Note: The "Version Found" column lists the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

  • No known issue with core

Change Log History

2016.3:
 * Version 8.0 (Rev. 11)
 * Enabled support for future devices
 
2016.2:
 * Version 8.0 (Rev. 10)
 * No changes
 
2016.1:

 * Version 8.0 (Rev. 10)
 * Delivering only Verilog simulation model, Stopped delivery of VHDL simulation model.
 
2015.4.2:

 * Version 8.0 (Rev. 9)
 * No changes
 
2015.4.1:

 * Version 8.0 (Rev. 9)
 * No changes
 
2015.4:

 * Version 8.0 (Rev. 9)
 * No changes
 
2015.3:

 * Version 8.0 (Rev. 9)
 * Delivering only VHDL simulation model, Stopped delivery of Verilog simulation model.
 * IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances
 
2015.2.1:
 * Version 8.0 (Rev. 8)
 * No changes
 
2015.2:
 * Version 8.0 (Rev. 8)
 * No changes
 
2015.1:

 * Version 8.0 (Rev. 8)
 * Delivering unencrypted simulation files.
 * Supported devices and production status are now determined automatically, to simplify support for future devices
 
2014.4.1:
 * Version 8.0 (Rev. 7)
 * No changes
 
2014.4:

 * Version 8.0 (Rev. 7)
 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
 * Internal device family change, no functional changes
 

 2014.3:
 * Version 8.0 (Rev. 6)
 * Reduced warnings in synthesis, no functional changes

2014.2:
 * Version 8.0 (Rev. 5)
 * Repackaged to improve internal automation, no functional changes.

2014.1:
 * Version 8.0 (Rev. 4)
 * Internal device family name change, no functional changes

2013.4:
 * Version 8.0 (Rev. 3)
 * Added support for UltraScale devices

2013.3:
 * Version 8.0 (Rev. 2)
 * Enhanced support for IP Integrator
 * Reduced warnings in synthesis and simulation
 * Added support for Cadence IES and Synopsys VCS simulators

2013.2:
 * Version 8.0 (Rev. 1)
 * Repackaged to enable internal version management, no functional changes.

2013.1:
 * Version 8.0
 * Native Vivado Release
 * Unused port SPRA and its associated parameters removed.

(c) Copyright 2002 - 2014 Xilinx, Inc. All rights reserved.

This file contains confidential and proprietary information of Xilinx, Inc. and is protected under U.S. and international copyright and other intellectual property laws.

DISCLAIMER
This disclaimer is not a license and does not grant any rights to the materials distributed herewith. Except as otherwise provided in a valid license issued to you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
(2) Xilinx shall not be liable (whether in contract or ttort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under or in connection with these materials, including for any direct, or any indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the
possibility of the same.

CRITICAL APPLICATIONS
Xilinx products are not designed or intended to be fail-safe, or for use in any application requiring fail-safe performance, such as life-support or safety devices or systems, Class III medical devices, nuclear facilities, applications related to the deployment of airbags, or any other applications that could lead to death, personal injury, or severe property or environmental damage (individually and collectively, "Critical Applications"). Customer assumes the sole risk and liability of any use of Xilinx products in Critical Applications, subject only to applicable laws and regulations governing limitations on product liability.

THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.


Revision History
04/03/2013 - Initial Release

 

AR# 54661
Date Created 02/28/2013
Last Updated 10/13/2016
Status Active
Type Release Notes
Devices
  • Zynq-7000
  • Kintex-7
  • Artix-7
  • Virtex-7
Tools
  • Vivado Design Suite
IP
  • Distributed Memory Generator