This answer record contains the Release Notes and Known Issues for the QSGMII Core and includes the following:
This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2013.1 and forward.
Please reference XTP025 - IP Release Notes Guide for past known issue logs and ISE support information.
LogiCORE QSGMII IP Page:
http://www.xilinx.com/content/xilinx/en/products/intellectual-property/qsgmii.html
General Information
Supported devices can be found in the following three locations:
For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado.
Version Table
This table correlates the core version to the first Vivado design tools release version in which it was included.
| Core Version | Vivado Tools Version |
|---|---|
| v3.3 (Rev. 6) | 2016.3 |
| v3.3 (Rev. 5) | 2016.2 |
| v3.3 (Rev. 4) | 2016.1 |
| v3.3 (Rev. 3) | 2015.4 |
| v3.3 (Rev. 2) | 2015.3 |
| v3.3 (Rev. 1) | 2015.2 |
| v3.3 | 2015.1 |
| v3.2 (Rev. 3) | 2014.3 |
| v3.2 (Rev. 2) | 2014.3 |
| v3.2 (Rev. 1) | 2014.2 |
| v3.2 | 2014.1 |
| v3.1 | 2013.4 |
| v3.0 | 2013.3 |
| v2.0 (Rev. 1) | 2013.2 |
| v2.0 | 2013.1 |
| v1.4 | 2012.3 |
| v1.3 | 2012.2 |
| v1.2 | 2012.1 |
General Guidance
The table below provides answer records for general guidance when using the LogiCORE QSGMII core.
| Answer Record | Title |
|---|---|
| (Xilinx Answer 38279) | Ethernet IP Solution Center |
| (Xilinx Answer 55077) | Ethernet IP Cores - Design Hierarchy in Vivado |
Known and Resolved Issues
The following table provides known issues for the ABC core, starting with v6.0, initially released in Vivado 2013.1.
Note: The "Version Found" column lists the version the problem was first discovered.
The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
| Answer Record | Title | Version Found | Version Resolved |
|---|---|---|---|
| (Xilinx Answer 61134) | QSGMII V3.2: Data mismatch or frame error seen with Example Test Bench Simulation when 3C Data is present in the Frame. | v3.2 | See Answer Record |
| (Xilinx Answer 60784) | GTP - Production reset DRP sequence could get in hung state that requires reconfiguration to recover | v3.2 | v3.2 (Rev. 1) |
| (Xilinx Answer 60084) | QSGMII v3.2 - UltraScale - PHY mode - Post Synthesis Simulation failures are seen | v3.2 | Not Resolved |
| (Xilinx Answer 58108) | Update to RX termination for 7 Series GTH | v1.4 | v3.0 |
| NA | Updates to 7 Series GTP/GTX/GTH Transceiver wrapper files for production support | v1.4 | v2.0 |
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 55077 | Ethernet IP - Design hierarchy in Vivado tools | N/A | N/A |
| 58108 | QSGMII v2.0 (Rev.1) and earlier - Update to RX termination for 7 Series GTH | N/A | N/A |
| 58460 | Ethernet 1000BASE-X PCS/PMA or SGMII v13.0 and QSGMII v2.0 rev1 and earlier - Update to 7 Series GTX Transceiver Port RXDFEXYDEN | N/A | N/A |
| 60084 | QSGMII v3.2 - UltraScale - PHY mode - Post Synthesis Simulation failures are seen | N/A | N/A |
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 45711 | LogiCORE IP QSGMII - Release Notes and Known Issues for 1.x | N/A | N/A |
| AR# 54668 | |
|---|---|
| Date | 10/13/2016 |
| Status | Active |
| Type | Release Notes |
| Tools |
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| IP |
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