UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 54673

MIG 7 Series DDR3 - Incorrect connection of write leveling debug signals in the ChipScope Write ILA when the debug signals are enabled

Description

Version Found: MIG 7 Series 1.8
Version Resolved: See (Xilinx Answer 45195)

When generating a MIG 7 Series DDR3 design with Debug Signals enabled, a few of the Write Leveling Calibration debug signals are not connected properly to the Write ILA ChipScope core. 

The incorrect connections are on 

  • wl_po_coarse_cnt,
  • wl_po_fine_cnt, 
  • rd_data_edge_detect_r,
    and 
  • wl_edge_detect_valid_r. 

This answer record shows how to manually correct these ILA connections until this issue is resolved in a future MIG 7 Series release.

Solution

The user_design/rtl/core_name.v module includes the connection of the debug signals to the ChipScope ILA cores.

Open this module and locate the "ILA for monitoring write path signals" section. 

The required connection updates are shown below.

The port numbers in comments are the old/incorrect connections.
 
//*******************************************************
   //     - ILA for monitoring write path signals,
   //       and synchronized read data
   //*******************************************************
 
   assign rd_data_edge_detect_r  = dbg_phy_wrlvl[67+:9]; //66
   assign wl_po_fine_cnt         = dbg_phy_wrlvl[76+:54]; //75
   assign wl_po_coarse_cnt       = dbg_phy_wrlvl[130+:27];  //129
 
   assign ddr3_ila_wrpath[10]    = dbg_phy_wrlvl[60]; //59  // wl_edge_detect_valid_r
   assign ddr3_ila_wrpath[96+:54] = dbg_phy_wrlvl[76+:54];  //75
   assign ddr3_ila_wrpath[150+:27]= dbg_phy_wrlvl[130+:27]; //129
 

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
70375 SDK 2017.2/.3 - Stepping over a source line causes core to stop at interrupt vector N/A N/A
70376 SDK, Bootgen - Offset parameter not handled in XIP mode N/A N/A
70373 Example Design - Simulating with the Zynq UltraScale+ MPSoC Verification IP N/A N/A
N/A N/A
70886 Partial Reconfiguration - DRC {[Constraints 18-4620] HDPostRouteDRC-07} can be skipped when the dedicated route is unused in the new configuration N/A N/A
70881 2018.1 Zynq UltraScale+ MPSoC: BootGen HSM Mode and Debug Mode output does not match with multiple .nky files N/A N/A
70889 Zynq UltraScale+ RFSoC: IP will not generate when internal PLL is used and DAC Sample rate is >6.4GSPS N/A N/A
N/A N/A
70402 2017.3/4 Zynq-7000: DTG does not build for single core Zynq design N/A N/A
70400 Vivado IP Flows - Synthesizing a Block design in non-project mode fails with ERROR: [Synth 8-439] module '' not found N/A N/A
70405 2018.1 Vivado IP Flows - Export_simulation only updates compile scripts not source files in ip and ipstatic dirctory N/A N/A
70403 GTY FRACXO - QPLL N Ratio for Higher Line Rates N/A N/A
7040 COREGEN: How to cascade the Serial and Parallel ROM-based Correlators N/A N/A
70501 2017.4 Tactical Patch - Place 30-935 Unroutable placement of IO loads (BITSLICE, IDDR/ODDR, ISERDES/OSERDES, etc). N/A N/A
70509 Vivado 2017.4 BBRAM programming fails when targeting VU13P device N/A N/A
70506 2017.4.1 Vivado - Vivado 2017.4 Update 1 (2017.4.1) Release Notes N/A N/A
70505 2017.4 Install - Some WebPACK devices unavailable in WebPACK installation N/A N/A
N/A N/A
70645 Zynq UltraScale+ MPSoC - Video Codec Unit (VCU) - What video formats are supported in GStreamer? N/A N/A
70648 Interlaken - OOBFC - 2017.4 and earlier - Out-of-Band Flow Control RX CRC Error can be seen in hardware N/A N/A
70646 2018.2 Vivado IP Flows - Packaged user IP does not deliver sub core IP that are instantiated under a conditional statement N/A N/A
70644 2018.x Vivado Synthesis - Known Issues N/A N/A
N/A N/A
7074 2.1i Install: Startup splash screen appears, but then dissappears and install fails without errors N/A N/A
70481 DMA Subsystem for PCI Express - FAQs and Debug Checklist N/A N/A
70482 UltraScale FPGA Gen3 Integrated Block for PCI Express - FAQs and Debug Checklist N/A N/A
70487 Soft Error Mitigation IP - Kintex UltraScale KU085 SEM IP will not boot up properly N/A N/A
70480 Virtex-7 FPGA Gen3 Integrated Block for PCI Express - FAQs and Debug Checklist N/A N/A
70485 UltraScale+ GTH/GTY - how to update CPLL calibration settings during a rate change N/A N/A
70483 UltraScale+ PCI Express Integrated Block - FAQs and Debug Checklist N/A N/A
7048 4.2i Foundation - If Windows NT was pre-installed on a computer, that PATH variable may need to be manually updated N/A N/A
70581 LogiCORE IP MIPI D-PHY Controller v4.0 (rev.1) (or MIPI CSI-2 Receiver Subsystem v3.0 (Rev. 1)) - Why do I see SoT/ECC/CRC errors on MIPI RX IP targeting UltraScale+ devices? N/A N/A
70589 Design Advisory for Zynq UltraScale+ MPSoC PS SYSMON, Vivado 2017.4 - PS SYSMON might temporarily show incorrect readings after FSBL/boot N/A N/A
70586 SMPTE UHD-SDI RX Subsystem v1.0 (Rev. 1) - Why is the ST352 valid bit toggling for 1080i59.94 when using the Blackmagic Designs ATEM 4k for the SDI Source? N/A N/A
N/A N/A
70009 2017.1-2017.4 Zynq UltraScale+ MPSoC: Linux causes a hang in RPU code which was running without issue until Linux loaded N/A N/A
70007 2017.3 Zynq UltraScale+ MPSoC: Xen Ethernet passthrough fails in PetaLinux N/A N/A
70000 2017.3 Vivado Simulator - xsc compiler is not working on Ubuntu N/A N/A
70008 Example Designs - Simulating with the AXI Verification IP N/A N/A
70005 2017.2/3 Zynq UltraScale+ MPSoC: FSBL Boot image with Key Rolling causes XFSBL Tag Mismatch error N/A N/A
70006 DDR4 Memory Controller - DDR4 Interface Potentially Fails All Zero Pattern Post Calibration N/A N/A
70004 Blink LED in Platform Cable USB II with Vivado Hardware Manager N/A N/A
7000 FPGA/Design Compiler - Using Synopsys DesignWare libraries compiled for 1998.02/A2.1i and 1997.08/A2.1i N/A N/A
70100 HDMI Transmitter (TX) Subsystem v2.0 - Why do I sometimes have problems transmitting HBR Audio? N/A N/A
70101 SDK 2017.3 - Release Notes and Known Issues N/A N/A
70104 2017.3 10/25G and 40/50G Ethernet Subsystems - stat_rx_bad_preamble and stat_rx_bad_sfd do not always assert N/A N/A
7010 Foundation schematic editor 2.1i: Some schematic components do not print out properly N/A N/A
70245 ISE S6 VM - Virtual Machine clock issues N/A N/A
70246 ISE S6 VM - Cannot access the internet from the Virtual Machine N/A N/A
70243 ISE S6 VM - Cannot enable networking for an ISE Virtual Machine N/A N/A
70244 ISE S6 VM - ISE will not launch from shortcuts or from the VirtualBox GUI N/A N/A
70241 ISE S6 VM - Cannot see the bottom of the Xilinx Simulation Library Compilation Wizard window N/A N/A
70249 ISE S6 VM - File/Folder deleted from shared folder does not get moved to the Virtual Machine's trash N/A N/A
70242 ISE S6 VM - Uninstallation process did not remove all files N/A N/A
70247 ISE S6 VM - Project Navigator windows does not resize or maximize properly N/A N/A
70240 ISE S6 VM - Accessing the ISE S6 VM on another User account N/A N/A
70248 ISE S6 VM - Some files in the shared folder cannot be deleted N/A N/A
7024 4.2i Foundation - "ERROR:basilisk:6 - Problem encountered invoking program 'm1map'..." N/A N/A
70347 Vivado IP Integrator - IRQ_F2P port is not getting populated correctly with vector N/A N/A
7034 Virtex: Is it possible to remove Vccint while applying Vcco? N/A N/A
70854 Zynq UltraScale+ MPSoC - DMA/Bridge Subsystem for PCI Express - PL Bridge Root Port - IP Setup tips for use with the PL PCIe Root Port driver N/A N/A
70852 AXI Sideband Formatter Utility IP Release Notes and Known Issues N/A N/A
N/A N/A
70915 Long Form Answer Record (LFAR): Eye Qualification with GT Debugger N/A N/A
70913 2014.2 Vivado IP Flows - Simple Processing System IP change causes synthesis to go out of date even if the changed options should only effect the exported xml and ps7_init for SDK N/A N/A
70919 Virtex UltraScale+ HBM Controller - Timing Violations on ARESET_N path N/A N/A
70912 2018.1 Vivado IP Flows - Validation fails for module reference block - [axi_bram_cntlr-1] Port-A interface property is not defined N/A N/A
70910 2018.2 Vivado IP Flows - I am not able to view the customization for a core if the IP is no longer available in the IP catalog N/A N/A
N/A N/A
70079 2017.1 Vivado IP Flows - Migrating a Vivado project with a BD to Vivado 2017.1 causes module references files to be stale N/A N/A
70076 2017.2 Vivado IP Flows - Implementation generates warning about IP instances of a BD being locked: [BD 41-1661] One or more IPs have been locked in the design N/A N/A
70077 2017.2 Licensing - Vivado license message incorrectly reports that it is looking for a license based on a feature which includes the package N/A N/A
70075 2017.x Vivado - Vivado cannot find math_real and math_complex in IEEE library: CRITICAL WARNING: [HDL 9-104] N/A N/A
70072 2017.3 Vivado IP Integrator - Block automation gives: ERROR: [BD 41-1273] Error running apply_rule TCL procedure: invalid msg id: a dash is required between the system alias and numeric id: e.g. "alias-100" N/A N/A
70073 Vivado - When I open a synthesized netlist, the displayed hierarchy is based on the current HDL and not just the hierarchy of the netlist N/A N/A
70070 Vivado IP Integrator - Is there a way to get comments added to IP integrator to be written out next to a particular instance in the HDL file N/A N/A
70078 2017.2 Vivado IP Flows - IP Packager is adding extra files to my IP when I manually add a file to a file group N/A N/A
70071 2017.4 Vivado - IDS_lite directory is not longer added to LD_LIBRARY_PATH or PATH variables in the Vivado loader script N/A N/A
7007 FPGA Express: MAP ERROR:baste:26 - The TBUFs "X" and "Y" drive the same output signal N/A N/A
70994 LogiCORE UHD-SDI GT - Why does the UHD-SDI GT wrapper fail to implement when selecting a multi-link configuration? N/A N/A
N/A N/A
70455 2017.4 Vivado Simulator Tactical Patch - crash on some machines when exiting the simulation N/A N/A
70452 2017.4 Install - Does Vivado have a silent installation option to add/remove Design tools and devices from command line? N/A N/A
70450 2017.4 - SDAccel - Frequency Scaling of Kernel Clock not applied N/A N/A
N/A N/A
70514 HDMI Transmitter and Receiver Subsystem - Where can I find an HDMI Compliant Reference Schematic? N/A N/A
70511 2017.4 10G/25G Ethernet SubSystem - AXI4-Lite - Errors using AXI4-Lite interface N/A N/A
70515 ZCU102; ZCU106 - HDMI Transmitter Subsystem - Why do I have problems with connecting to some HDMI Sinks? N/A N/A
7051 4.1i Licensing - Floating licenses for computer names with spaces in them cause a "Not a valid server host name" error N/A N/A
70611 PG288 for AXI Multi-Channel DMA unclear about clock relationship in synchronous mode N/A N/A
70619 TX configurable driver spreadsheet and TX over-equalization N/A N/A
N/A N/A
707 FITNET will not use PIN 1 (MR) even if MRINPUT=ON was specified in Viewlogic N/A N/A
70593 2017.4 SMPTE UHD-SDI RX Subsystem v1.0 (Rev. 1) - Patch Updates for the SMPTE UHD-SDI RX Subsystem v1.0 (Rev. 1) N/A N/A
70591 LogiCORE IP MIPI D-PHY v4.0 - Can I change IDELAY tap values on the fly for MIPI D-PHY IP v4.0? (IP targeting 7 Series devices) N/A N/A
70599 SDK - How to use a patched driver N/A N/A
70592 UltraScale/UltraScale+ Built In FIFO - Behavior of the RDRSTBUSY and WRRSTBUSY signals N/A N/A
70597 Vivado 2017.4 - ERROR: [Common 17-56] 'list_property' expects exactly one object got '2'. N/A N/A
70595 2017.4 IP-Processing System - Upgrade of the MPSoC design is not happening correctly. N/A N/A
70596 2017.4.1 QSPI device is not detected for some designs in Zynq 7000 N/A N/A
AR# 54673
Date 08/18/2014
Status Active
Type Known Issues
Devices
  • Artix-7
  • Kintex-7
  • Virtex-7
IP
  • MIG 7 Series
Page Bookmarked