AR# 54673


MIG 7 Series DDR3 - Incorrect connection of write leveling debug signals in the ChipScope Write ILA when the debug signals are enabled


Version Found: MIG 7 Series 1.8
Version Resolved: See (Xilinx Answer 45195)

When generating a MIG 7 Series DDR3 design with Debug Signals enabled, a few of the Write Leveling Calibration debug signals are not connected properly to the Write ILA ChipScope core. 

The incorrect connections are on 

  • wl_po_coarse_cnt,
  • wl_po_fine_cnt, 
  • rd_data_edge_detect_r,
  • wl_edge_detect_valid_r. 

This answer record shows how to manually correct these ILA connections until this issue is resolved in a future MIG 7 Series release.


The user_design/rtl/core_name.v module includes the connection of the debug signals to the ChipScope ILA cores.

Open this module and locate the "ILA for monitoring write path signals" section. 

The required connection updates are shown below.

The port numbers in comments are the old/incorrect connections.
   //     - ILA for monitoring write path signals,
   //       and synchronized read data
   assign rd_data_edge_detect_r  = dbg_phy_wrlvl[67+:9]; //66
   assign wl_po_fine_cnt         = dbg_phy_wrlvl[76+:54]; //75
   assign wl_po_coarse_cnt       = dbg_phy_wrlvl[130+:27];  //129
   assign ddr3_ila_wrpath[10]    = dbg_phy_wrlvl[60]; //59  // wl_edge_detect_valid_r
   assign ddr3_ila_wrpath[96+:54] = dbg_phy_wrlvl[76+:54];  //75
   assign ddr3_ila_wrpath[150+:27]= dbg_phy_wrlvl[130+:27]; //129

Linked Answer Records

Master Answer Records

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9602 3.x FPGA Express - Error: "Syntax error at or near 'parameter' (file: 'path' line:#) (VE-0)" N/A N/A
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9665 1.0 eProduct - What is the flow for simulation with VHDL Coregen and Schematic? N/A N/A
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9641 3.1i SP1 - 3.1i Service Pack 1 update N/A N/A
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72806 2019.1 Linux: MACB + PL PCS PMA link issues on Zynq UltraScale+ MPSoC N/A N/A
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72139 2019.x Zynq UltraScale+ MPSoC: Yocto or PetaLinux return warnings when you enable libmali with the fbdev windowing system N/A N/A
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72486 2019.1 RFSoC - RF Analyzer Tutorial N/A N/A
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72586 2018.x Vivado Synthesis - Incorrect Logic Generation for FSM N/A N/A
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72745 2019.x Vivado Simulation - Known Issues N/A N/A
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AR# 54673
Date 08/18/2014
Status Active
Type Known Issues
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