AR# 54673

MIG 7 Series DDR3 - Incorrect connection of write leveling debug signals in the ChipScope Write ILA when the debug signals are enabled

Description

Version Found: MIG 7 Series 1.8
Version Resolved: See (Xilinx Answer 45195)

When generating a MIG 7 Series DDR3 design with Debug Signals enabled, a few of the Write Leveling Calibration debug signals are not connected properly to the Write ILA ChipScope core. 

The incorrect connections are on 

  • wl_po_coarse_cnt,
  • wl_po_fine_cnt, 
  • rd_data_edge_detect_r,
    and 
  • wl_edge_detect_valid_r. 

This answer record shows how to manually correct these ILA connections until this issue is resolved in a future MIG 7 Series release.

Solution

The user_design/rtl/core_name.v module includes the connection of the debug signals to the ChipScope ILA cores.

Open this module and locate the "ILA for monitoring write path signals" section. 

The required connection updates are shown below.

The port numbers in comments are the old/incorrect connections.
 
//*******************************************************
   //     - ILA for monitoring write path signals,
   //       and synchronized read data
   //*******************************************************
 
   assign rd_data_edge_detect_r  = dbg_phy_wrlvl[67+:9]; //66
   assign wl_po_fine_cnt         = dbg_phy_wrlvl[76+:54]; //75
   assign wl_po_coarse_cnt       = dbg_phy_wrlvl[130+:27];  //129
 
   assign ddr3_ila_wrpath[10]    = dbg_phy_wrlvl[60]; //59  // wl_edge_detect_valid_r
   assign ddr3_ila_wrpath[96+:54] = dbg_phy_wrlvl[76+:54];  //75
   assign ddr3_ila_wrpath[150+:27]= dbg_phy_wrlvl[130+:27]; //129
 

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
54065 14.4 SysGen - "xlSyncLevels threw in xlMungeMaskParams: Maximum recursion limit of 500 reached..." N/A N/A
54063 14.4 System Generator for DSP - Recursion Limit Error N/A N/A
54069 LogiCORE IP Color Filter Array Interpolation (CFA) v3.0 and v4.0 - Why does the CFA fail to generate if the maximum number of columns or rows is set to larger than 1024 when using the EDK pcore in XPS? N/A N/A
N/A N/A
54577 Install - Is WebPack version 6.2 the same as Foundation ISE version 6.2 and how to get the registration ID for 6.2 ISE ? N/A N/A
N/A N/A
54678 Release Notes and Known Issues for LogiCORE IP AXI Bus Functional Models (AXI BFM) for Vivado 2012.4 and Forward N/A N/A
54677 Vivado IP Flows - Generated IP target files delivered in Vivado are always READ ONLY in the Vivado Text Editor N/A N/A
54673 MIG 7 Series DDR3 - Incorrect connection of write leveling debug signals in the ChipScope Write ILA when the debug signals are enabled N/A N/A
54205 14.x XPower Analyzer - "EXCEPTION:Pds:Pds_PdlBlock.c:319:1.24 - Mode mismatch error." N/A N/A
54206 PlanAhead - MYXILINX enviroment variable is not loaded by the PlanAhead tool N/A N/A
54209 Virtex-7 FPGA VC707 Evaluation Kit - UG885 (v1.2) - EMCCLK settings for Linear BPI Flash Memory configuration incorrect N/A N/A
5420 Alliance/Foundation 1.5i: Icons in start menu do not bring up the software. Can't find execuatble. N/A N/A
N/A N/A
54445 LogiCORE IP I/O Module - Release Notes and Known Issues for Vivado 2013.4 and older tool versions N/A N/A
54446 Zynq Processing System 7 IP - Release Notes and Known Issues for Vivado 2013.4 and older tool versions N/A N/A
54444 LogiCORE IP AXI Timebase Watchdog Timer (WDT) - Release Notes and Known Issues for Vivado 2013.4 and older tool versions N/A N/A
54449 LogiCORE IP Controller Area Network (CAN) - Release Notes and Known Issues for Vivado 2016.3 and older tool versions N/A N/A
54442 LogiCORE IP AXI Performance Monitor - Release Notes and Known Issues for Vivado 2013.4 and older tool versions N/A N/A
54447 LogiCORE IP AXI Streaming FIFO - Release Notes and Known Issues for Vivado 2013.4 and older tool versions N/A N/A
54448 LogiCORE IP AXI Video Direct Memory Access - Release Notes and Known Issues for Vivado 2013.1 and newer tool versions N/A N/A
N/A N/A
54544 LogiCORE Video to SDI TX Bridge Core - Release Notes and Known Issues for the Vivado 2013.1 tool and later versions N/A N/A
54545 LogiCORE SDI RX to Video Bridge - Release Notes and Known Issues for the Vivado 2013.1 tool and later versions N/A N/A
54543 LogiCORE IP SPDIF/AES3 - Release Notes and Known Issues for Vivado 2013.1 and newer tool versions N/A N/A
54540 LogiCORE IP Video Scaler - Release Notes and Known Issues for Vivado 2013.1 and newer tool versions N/A N/A
54548 Video over IP FEC Receiver (VoIP FEC RX) - Release Notes and Known Issues for the Vivado 2013.1 tool and later versions N/A N/A
54549 LogiCORE IP Video over IP FEC Transmitter (VoIP FEC TX) - Release Notes and Known Issues for the Vivado 2015.1 tool and later versions N/A N/A
5454 4.2i Foundation Library Manager - When I attach a library to another project, unexpanded block errors occur in implementation tools N/A N/A
54174 Virtex-7 FPGA Gen3 Integrated Block for PCI Express v1.4 (ISE 14.4/Vivado 2012.4) - GTX transceiver CPLL can become inoperative on certain conditions N/A N/A
54177 2012.4 Vivado Implementation: Automatic insertion of BUFG on high fanout reset signals N/A N/A
54173 ISE Design Suite - The supported Zynq devices are incorrectly listed on the ISE Design Suite product page N/A N/A
5417 LogiCORE Direct Digital Synthesis (DDS) - What controls the effective Signal-to-Noise Ratio (SNR) of the DDS Core? N/A N/A
54274 Zynq-7000 Example Design - IP Integrator AXI3 Master N/A N/A
54279 Kintex-7 FPGA KC705 Evaluation Kit - Interface Test Designs N/A N/A
54276 CONSTRAINTS : How can I constrain asynchronous paths from the clock resources? N/A N/A
N/A N/A
54038 Vivado - ERROR: [Common 17-161] Invalid option value 'BITSTREAM.CONFIG.UNUSEDPIN' specified for 'name' N/A N/A
54036 Zynq-7000 SoC ZC706 - UG963 (v1.0) - SW11 switch settings incorrect for SD card boot N/A N/A
54037 Zynq-7000 SoC ZC706 - UG961 (v1.0) - SW11 switch settings incorrect for SD card boot N/A N/A
5403 Constraints - Is there a way to add internal pull-ups/pull-downs in a device using the UCF (User Constraints File) or Constraints Editor? N/A N/A
54651 32/64-bit Initiator/Target for PCI (7 series) - IP Release Notes and Known Issues for Vivado 2013.1 and newer tool versions N/A N/A
N/A N/A
54712 VITA 57.1 FMC standard - FMC_VIO_B_M2C signal is supplied by the FMC card N/A N/A
54710 MIG 7 Series - DDR3 - Controller hangs on a read-modify-write operation N/A N/A
N/A N/A
54810 Vivado - Unable to use (read-only) XCI IP core files (under version control) in Vivado non-project mode N/A N/A
54811 v1.03a - axi_intc - Fast interrupt does not work with AXI_INTC N/A N/A
54817 ILA 2.0 - Debug IP from 2012.x does not appear in 2013.1 N/A N/A
54813 IP Release Notes and Known Issues for LogiCORE IP AXI4-Stream Interconnect Cores for Vivado 2013.1 tools and newer tool versions N/A N/A
54958 Design Assistant for Vivado Synthesis - Help with synth_design switches and their description N/A N/A
54956 14.5 iMPACT - iMPACT is unable to play the SVF file with an exception "Data Mismatch" N/A N/A
54953 Test AR 2 for CMS Testing (updated 3/20/2013) N/A N/A
54951 Vivado - How can I report BUFHCE usage in the device? N/A N/A
54952 Test AR (take 2) N/A N/A
N/A N/A
54682 IP Release Notes and Known Issues for LogiCORE AXI DMA Core for Vivado 2013.1 and newer tool versions N/A N/A
54687 14.4 EDK - SDK not able to build a BSP for Zynq devices when used from the PlanAhead tool N/A N/A
54685 IP Release Notes and Known Issues for LogiCORE AXI CDMA for Vivado 2013.1 and Forward N/A N/A
54683 2012.4 Vivado Implementation Tools - How do I do manual routing in Vivado GUI? N/A N/A
N/A N/A
54782 Vivado - In the Vivado text editor, is there a way to toggle the case of a group of characters? N/A N/A
54785 LogiCORE IP Tri-Mode Ethernet MAC v5.5 and earlier - IFG Adjust values that are smaller than 9 will result in TX IFG of 12 when core is generated with half duplex support N/A N/A
N/A N/A
54143 Kintex-7 FPGA Embedded Kit - Compiling webserver application cannot find “lmfsimage” N/A N/A
54140 7 Series Transceivers - What are the termination values of transceiver ports before the device is configured? N/A N/A
54146 Logicore IP Aurora 8B10B/64B66B - Recommendation for new designs N/A N/A
N/A N/A
54317 Vivado - Non-project IP core "does not match the current project part" N/A N/A
N/A N/A
54418 LogiCORE IP AXI BRAM Interface Controller - Release Notes and Known Issues for Vivado 2013.4 and older tool versions N/A N/A
54419 LogiCORE IP AXI External Peripheral Controller (EPC) - Release Notes and Known Issues for Vivado 2013.4 and older tools versions N/A N/A
54414 LogiCORE IP MicroBlaze Micro Controller System (MCS) - Release Notes and Known Issues for Vivado 2013.4 and older tool versions N/A N/A
54415 LogiCORE IP Mailbox - Release Notes and Known Issues for Vivado 2013.4 and older tool versions N/A N/A
54412 IP Release Notes and Known Issues for LogiCORE AXI TFT Controller for Vivado 2013.4 and older tool versions N/A N/A
54413 LogiCORE IP MicroBlaze Debug Module (MDM) - Release Notes and Known Issues for Vivado 2013.4 and older tool versions N/A N/A
5441 LogiCORE PCI - What addressing mode is supported during memory burst transactions? N/A N/A
54556 14.4 SDK - Program FPGA button is unresponsive in Zynq projects N/A N/A
54553 2012.4/14.4 - XPS - Enabling GPIO on EMIO Interface Not Possible When Using Processing System 7 v4.02a N/A N/A
54551 Vivado Synthesis - How does Vivado Synthesis treat imported core netlists? N/A N/A
54559 14.4 - EDK - XPS - How can I make the AXI Datamover's M_AXIS_MM2S and S_AXIS_S2MM bus interfaces external? N/A N/A
N/A N/A
54282 7 series GTX - What is the power consumption of the eye scan circuit? N/A N/A
54285 Soft Error Mitigation (SEM) v3.5 - Requirements for Support of Larger Densities of SPI Flash N/A N/A
54283 2013.2 Vivado - Vivado interprets EDIF netlist keywords as case sensitive N/A N/A
54284 2012.x - Signals created with a generate statement not saved to WFCG file N/A N/A
N/A N/A
54380 14.4 - XPS - XADC Instantiation option is grayed out in the config IP GUI for AXI 7 Series DDRx IP N/A N/A
54381 Xilinx Programming Cables - Platform Cable USB and Parallel Cable IV - Driver install FAQ N/A N/A
54384 MIG 7 Series DDR3 - changing DATA_PATTERN in sim_tb_top.v does not work as expected N/A N/A
54382 Digilent Programming Cables - Driver Install FAQ N/A N/A
54383 Artix-7 FPGA AC701 Evaluation Kit - Interface Test Designs N/A N/A
N/A N/A
54044 Vivado 2012.4/ISE 14.4 - Device Pack (2012.4.1) Release Notes N/A N/A
54042 14.5 Install - I am unable to download the ISE 14.5 Design Suites install image N/A N/A
N/A N/A
54667 LogiCORE IP 1G/2.5G Ethernet PCS/PMA or SGMII - Release Notes and Known Issues for Vivado 2013.1 and newer tools N/A N/A
54668 LogiCORE IP QSGMII - Release Notes and Known Issues for Vivado 2013.1 and Forward N/A N/A
54666 LogiCORE IP XAUI - Release Notes and Known Issues for Vivado 2013.1 and newer tool versions N/A N/A
54663 LogiCORE IP FIFO Generator - Release Notes and Known Issues for Vivado 2013.1 and newer tools N/A N/A
AR# 54673
Date 08/18/2014
Status Active
Type Known Issues
Devices
IP