AR# 54673

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MIG 7 Series DDR3 - Incorrect connection of write leveling debug signals in the ChipScope Write ILA when the debug signals are enabled

Description

Version Found: MIG 7 Series 1.8
Version Resolved: See (Xilinx Answer 45195)

When generating a MIG 7 Series DDR3 design with Debug Signals enabled, a few of the Write Leveling Calibration debug signals are not connected properly to the Write ILA ChipScope core. 

The incorrect connections are on 

  • wl_po_coarse_cnt,
  • wl_po_fine_cnt, 
  • rd_data_edge_detect_r,
    and 
  • wl_edge_detect_valid_r. 

This answer record shows how to manually correct these ILA connections until this issue is resolved in a future MIG 7 Series release.

Solution

The user_design/rtl/core_name.v module includes the connection of the debug signals to the ChipScope ILA cores.

Open this module and locate the "ILA for monitoring write path signals" section. 

The required connection updates are shown below.

The port numbers in comments are the old/incorrect connections.
 
//*******************************************************
   //     - ILA for monitoring write path signals,
   //       and synchronized read data
   //*******************************************************
 
   assign rd_data_edge_detect_r  = dbg_phy_wrlvl[67+:9]; //66
   assign wl_po_fine_cnt         = dbg_phy_wrlvl[76+:54]; //75
   assign wl_po_coarse_cnt       = dbg_phy_wrlvl[130+:27];  //129
 
   assign ddr3_ila_wrpath[10]    = dbg_phy_wrlvl[60]; //59  // wl_edge_detect_valid_r
   assign ddr3_ila_wrpath[96+:54] = dbg_phy_wrlvl[76+:54];  //75
   assign ddr3_ila_wrpath[150+:27]= dbg_phy_wrlvl[130+:27]; //129
 

Linked Answer Records

Master Answer Records

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9647 *Obselete* 3.1i JTAG Programmer - Dr. Watson error encountered while trying to generate an SVF program device N/A N/A
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9618 3.1i Design Manager - Implementing Guided MAP on Virtex designs does not work N/A N/A
9648 3.1i D_IP1 Virtex-II, CORE Generator - The output initialization for a single-port block RAM VHDL behavioral model is incorrect N/A N/A
9672 3.1i Service Pack Install - Canceling the Service Pack Install gives message "Install Completed Successfully." N/A N/A
9632 FPGA Configuration - Does Xilinx support the I2C standards for configuration? N/A N/A
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9603 3.1i Virtex PAR - Designs with a large number of SRL16s may see poor PAR performance. N/A N/A
9697 5.1i CORE Generator - What is the role of COE and MIF files for Virtex and Virtex-II Cores? N/A N/A
9657 3.1i Virtex PAR - Warning: place 1795: The placement of the source component must be in the same CLB column as the output LVDS pair N/A N/A
9684 5.1i Timing Analyzer/Trace (TRCE) - Paths that lead to and from block RAM are being incorrectly constrained (BRAMS_PORTA) N/A N/A
9602 3.x FPGA Express - Error: "Syntax error at or near 'parameter' (file: 'path' line:#) (VE-0)" N/A N/A
9612 COREGEN - How to implement a 256 point FFT using the 1024 point FFT core N/A N/A
9627 1.0 eProduct, LogiBLOX - How do I add LogiBLOX in ViewDraw's custom menu? N/A N/A
9654 CPLD XC9500- XC9500 device (any density) fails to configure properly after power-up. N/A N/A
9681 3.1i Virtex-E PAR - Use of USELOWSKEWLINES impacts runtime and QOR N/A N/A
9665 1.0 eProduct - What is the flow for simulation with VHDL Coregen and Schematic? N/A N/A
9695 ISE Text Editor - Is the ISE Text Editor accessible from outside Project Navigator? N/A N/A
9641 3.1i SP1 - 3.1i Service Pack 1 update N/A N/A
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72805 Zynq UltraScale+ MPSoC PS SYSMON Clocking N/A N/A
72808 UltraScale+ GTY - Adaptation Loop Override Attributes N/A N/A
72806 2019.1 Linux: MACB + PL PCS PMA link issues on Zynq UltraScale+ MPSoC N/A N/A
72136 Zynq UltraScale+: PS GEM - reason for multiple duplicate packets in custom software driver N/A N/A
72139 2019.x Zynq UltraScale+ MPSoC: Yocto or PetaLinux return warnings when you enable libmali with the fbdev windowing system N/A N/A
72130 /libstdc++.so.6: version `CXXABI_1.3.11' not found N/A N/A
72230 UltraScale/UltraScale+ - RLDRAM3 IP - Known Issues with RLDRAM3 and SEM IP Interaction N/A N/A
72238 Zynq UltraScale+ MPSoC - Vivado Readback Verify fails when PL SYSMON is configured via APB Slave Interface N/A N/A
72237 SDAccel 2019.x - Known Issues N/A N/A
72233 Video Processing Subsystem v2.0 - PG231 - Why does the SDK project for the example design fail to generate in the 2018.3 release and later versions? N/A N/A
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72379 2019.1 Zynq UltraScale+ MPSoC: LwIP Support for A53 32-bit Toolchain N/A N/A
72377 2019.x Zynq-7000, Zynq UltraScale+ MPSoC: Yocto or PetaLinux build with petalinux-image-full images hangs without reaching Linux boot login prompt N/A N/A
72376 2018.x-2019.1 Zynq UltraScale+ MPSoC: USB core reset in Linux can cause issues with USB device connected if it was previously powered in U-boot N/A N/A
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72987 ZYNQ UltraScale+ VCU DDR4 Controller v1.0 - VCU DDR4 Controller IP synthesis errors when running the generate output products operation in Vivado 2019.1 N/A N/A
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72409 2019.1 Zynq UltraScale+ MPSoC: Linux USB 3.0 device mode does not work N/A N/A
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72405 ZCU111 2019.1 BSP patch files N/A N/A
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72404 Simulation Libraries failures for Vivado 2019.1 N/A N/A
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72509 2019.1 Documentation Navigator - SSL error when running Documentation Navigator in Ubuntu 18 N/A N/A
72506 2019.1 - SMPTE UHD-SDI RX Subsystem v2.0 (Rev. 3) - Patch Updates for the SMPTE UHD-SDI RX Subsystem v2.0 (Rev. 3) N/A N/A
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72503 2018.3 Zynq UltraScale+ MPSoC VCU - How do I improve the quality of the video when using the VCU Encoder to encode video content containing scrolling text? N/A N/A
7250 4.2i Foundation Simulator - Memory write address exceeds defined memory bounds N/A N/A
72487 Vivado 2019.1 Tactical Patch - Unable to close timing on XDNN design on VU13P device N/A N/A
72480 VCU129 - Early Boards Cannot read status from SFP28s, SFP56s and SI5348 N/A N/A
72486 2019.1 RFSoC - RF Analyzer Tutorial N/A N/A
7248 4.2i Foundation Schematic - "Warning: Multiple drivers or sourceless/loadless nets detected..." N/A N/A
72588 Design Advisory for Zynq UltraScale+ MPSoC/RFSoC: Encrypt Only Boot Mode - Unauthenticated Boot and Partition Headers N/A N/A
72586 2018.x Vivado Synthesis - Incorrect Logic Generation for FSM N/A N/A
72640 Alveo Data Center Accelerator Card - Card might not return after PCI Express In-Band Hot reset on AMD EPYC Host N/A N/A
72645 UltraScale+ GTM - Instructions for migrating to Vivado 2019.1.2/2019.1.3 N/A N/A
72747 DMA Subsystem for PCI Express in "AXI-Bridge" mode (Vivado 2019.1) - "NUM_READ_OUTSTANDING" and "NUM_WRITE_OUTSTANDING" parameters of M_AXI_B port reset to "2" after validate BD is executed in IP Integrator N/A N/A
72745 2019.x Vivado Simulation - Known Issues N/A N/A
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72007 2018.3 Zynq UltraScale+ MPSoC: DTG does not build with Video Processing System design N/A N/A
72000 AXI CAN-FD Linux driver does not work for Flexible Datarate N/A N/A
72003 Design Advisory for Zynq UltraScale+ MPSoC/RFSoC - MIO26 cannot be used for GEM TSU_REF_CLK N/A N/A
72106 2018.3 Zynq UltraScale+ MPSoC: Linux MDC clock divisor in GEM might be incorrect because PCLK value is not accessible N/A N/A
72103 2018.3.1 Vivado - Vivado 2018.3 Update 1 (2018.3.1) Release Notes and Known Issues N/A N/A
72108 UHD-SDI GT v1.0 (Rev 3) - Only the first link is working when I select more than one link in the UHD-SDI GT core N/A N/A
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72107 2018.3 Yocto: Why does the base device-tree not build with symbols when using YAML_ENABLE_DT_OVERLAY = "1" N/A N/A
72916 UltraScale/UltraScale+ (Vivado 2019.1) - PCI Express Integrated Block does not respond correctly to the "interrupt_disable" bit setting for Legacy interrupts N/A N/A
72910 Vitis 2019.2 - Eclipse GUI issues due to incompatible GTK version on Ubuntu 16.04 machines N/A N/A
7291 3.x FPGA Express - BSCAN_VIRTEX is removed from my design without warning N/A N/A
72075 UHD-SDI GT v1.0 (Rev 3) - Patch Update for UHD-SDI GT in Vivado 2018.3 N/A N/A
AR# 54673
Date 08/18/2014
Status Active
Type Known Issues
Devices
IP
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