AR# 54678


Release Notes and Known Issues for LogiCORE IP AXI Bus Functional Models (AXI BFM) for Vivado 2012.4 and Forward


This answer record contains the Release Notes and Known Issues for LogiCORE IP AXI Bus Functional Models (AXI BFM) and includes the following:

  • General Information
  • Design Assistant
  • Known and Resolved Issues
  • Revision History

This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2013.1 and forward.

Please reference XTP025 - IP Release Notes Guide for past known issue logs and ISE support information.

LogiCORE IP AXI Bus Functional Models Core IP Page:


General Information

Supported Devices can be found in the following three locations:

For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado.

Version Table

This table correlates the core version to the first Vivado design tools release version in which it was included.

Core VersionVivado Tools Version
v5.0 (Rev. 7)2015.3
v5.0 (Rev. 6)2015.2
v5.0 (Rev. 5)2015.1
v5.0 (Rev. 4)2014.3
v5.0 (Rev. 3)2014.2
v5.0 (Rev. 2)2014.1
v5.0 (Rev. 1)2013.4



General Guidance

For general guidance on how to use this core, please refer to LogiCORE IP AXI Bus Functional Models Data Sheet for more details.

For Licensing, please refer to (Xilinx Answer 61473).

Design Assistant

Here are some example designs and extra information for the core:

Article Number

Article Title
(Xilinx Answer 62769)2014.2 Vivado - AXI BFM IPI example design
(Xilinx Answer 57551)Example Design - Simulating the AXI DMA core in IPI using the AXI BFMs
(Xilinx Answer 57069)14.x/2013.x (Linux) - AXI BFM - License Issues with 3rd party Simulators
(Xilinx Answer 55464)AXI BFM - Licensing Information
(Xilinx Answer 56383)2013.1 Vivado IPI - Example of using AXI BFM models in IPI
(Xilinx Answer 52581)2012.x - AXI BFM - Tool Support for AXI Bus Functional Model

Known and Resolved Issues

The following table provides known issues for LogiCORE IP AXI Bus Functional Model core, starting with v3.0, initially released in Vivado 2012.4.

Note: The "Version Found" column lists the version the problem was first discovered.

The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions. Please also refer to Change log for more details.

Article Number

Article TitleVersion FoundVersion Resolved
(Xilinx Answer 67207)Vivado 2016.1 AXI BFM, Zynq BFM - AXI BFM and Zynq BFM do not correctly terminate WSTRBs of unaligned burst writes2016.1See Answer Record
(Xilinx Answer 63392)ModelSim DE/PE - How do I run the AXI BFM Example Design in Vivado 2014.4?2014.4See Answer Record
(Xilinx Answer 60841)2014.1 AXI BFM - ERROR: RVALID from slave is not zero (reset value) - AMBA AXI SPEC V2 - Section 11.1.2 Reset 2014.12014.3
(Xilinx Answer 59667)Vivado/ModelSim - ModelSim fails on PLI (AXI BFM) with "Error: (vsim-3193)" and "Error: (vsim-PLI-3002)"2013.2See Answer Record
(Xilinx Answer 56684)2013.x - How do you run AXI BFM simulation with NCSim? v4.1v5.0
(Xilinx Answer 58164)2013.x - How do you run AXI BFM simulation with VCS? v4.0N/A
(Xilinx Answer 52759)2012.2 Vivado IP Flows - Synthesizing the AXI BFM core results in "ERROR: [Designutils 20-414] HRTInvokeSpec : No Verilog or VHDL sources specified" 3.0N/A
(Xilinx Answer 54680)AXI Bus Functional Model v3.0 - Cannot generate this version in 14.4 Coregen/XPSv3.0N/A

Revision History:

04/03/2013 - Initial Release

AR# 54678
Date 06/10/2016
Status Active
Type Release Notes
Devices More Less
Tools More Less
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