This answer record contains the Release Notes and Known Issues for the GMII to RGMII IP Core and includes the following:
This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2013.1 and newer tool versions.
GMII to RGMII LogiCORE IP Page:
Supported Devices can be found in the following three locations:
For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado.
This table correlates the core version to the first Vivado design tools release version in which it was included.
|Vivado Tools |
|v4.0 (Rev. 7)||2018.3|
|v4.0 (Rev. 6)||2018.1|
|v4.0 (Rev. 5)||2017.4|
|v4.0 (Rev. 4)||2017.1|
|v4.0 (Rev. 3)||2016.1|
|v4.0 (Rev. 2)||2015.4|
|v4.0 (Rev. 1)||2015.3|
|v3.0 (Rev. 4)||2014.4|
|v3.0 (Rev. 3)||2014.3|
|v3.0 (Rev. 2)||2014.2|
|v3.0 (Rev. 1)||2014.1|
The table below provides answer records for general guidance when using the LogiCORE GMII to RGMII IP core.
|(Xilinx Answer 55248)||Vivado Timing and IP Constraints|
Known and Resolved Issues
The following table provides known issues for the LogiCORE GMII to RGMII IP core, starting with v1.0, initially released in Vivado 2013.1.
Note: The "Version Found" column lists the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
Please also refer to the Change Log in Vivado for details.
|Answer Record||Title||Version |
|NA||Bug Fix: Fix for synthesis failure where core is generated in Vivado with the name gmii_to_rgmii.||2017.4||2018.1|
|NA||Bug Fix: Changed REFCLK_FREQUENCY of delay elements in Zynq UltraScale+ devices to 374.953 MHz||2017.4||2018.1|
|NA||Bug Fix: Added synchronizers on gmii_rx_dv and gmii_rx_er to generate COL and CRS signals in gmii_clk domain.||2017.4||2018.1|
|NA||Bug Fix: Fix for BUFR along with BUFG combination is used in the RX_CLK path||2016.4||2017.1|