This answer record contains the Release Notes and Known Issues for the 40G/50G Ethernet Subsystem and includes the following:
This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2016.1 and forward.
40G/100G Ethernet Core LogiCORE IP Page:
https://www.xilinx.com/products/intellectual-property/ef-di-50gemac.html
General Information
Supported Devices can be found in the following three locations:
For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado.
Version Table
This table correlates the core version to the first Vivado design tools release version in which it was included.
| Core Version | Vivado Tool Version |
| v3.2 | 2020.2 |
| v3.1 | 2020.1 |
| v3.0 | 2019.2 |
| v2.5 | 2019.1 |
| v2.4 | 2018.3 |
| v2.3 (Rev. 3) | 2018.2 |
| v2.3 (Rev. 2) | 2018.1 |
| v2.3 (Rev. 1) | 2017.4 |
| v2.3 | 2017.3 |
| v2.2 | 2017.2 |
| v2.1 | 2017.1 |
| v2.0 (Rev. 1) | 2016.4 |
| v2.0 | 2016.3 |
| v1.1 | 2016.2 |
| v1.0 | 2016.1 |
General Guidance
The table below provides Answer Records for general guidance when using the LogiCORE 40G/100G Ethernet core.
| Article Number | Article Title |
|---|---|
| (Xilinx Answer 67675) | Simulation Speed Up |
| (Xilinx Answer 71820) | UltraScale/UltraScale+ Reset Sequence Requirements |
| (Xilinx Answer 69026) | Auto-Negotiation Link Bring up and Debug |
Known and Resolved Issues
The following table provides known issues for the 40G/50G High Speed Ethernet Subsystem, initially released in the Vivado 2016.1 tool.
Note: The "Version Found" column lists the version the problem was first discovered.
The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
| Answer Record | Title | Version Found | Version Resolved |
|---|---|---|---|
| (Xilinx Answer 75754) | GTM - Multi-lane core - Additional GT datapath resets needed after main sys_reset/gt_reset_all | v3.2 | See AR |
| (Xilinx Answer 70657) | 40G 256-bit AXI Stream Interface Example Design sometimes does not work in hardware | v2.3 (Rev. 1) | v2.3 (Rev. 2) |
| (Xilinx Answer 69612) | Update needed for intermittent link up if using Auto-Negotiation and Link Training | v2.0 | v2.3 |
| (Xilinx Answer 69568) | Incorrect Alignment Marker Spacing used if generating core with RS-FEC, but not enabling RS-FEC | v2.0 | v2.2 |
| (Xilinx Answer 68731) | 40G core, no support for -1 speed grade | v2.0 | v2.1 |
| (Xilinx Answer 67612) | Patch Updates for block lock issue in 40G core | v1.2 | v2.0 |
| (Xilinx Answer 67256) | How can the core be targeted to Kintex UltraScale/ Kintex UltraScale+ devices | v1.1 | v1.2 |
| AR# 54690 | |
|---|---|
| Date | 12/09/2020 |
| Status | Active |
| Type | Release Notes |
| IP | |