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AR# 54732

14.5 CORE Generator - Clocking Wizard and Aurora 8B10B cores add example design to project hierarchy

Description

When I generate the output files for a PLL or Aurora 8B10B core, the *_exdes.vhd example design source files are automatically added to my project hierarchy. 

Every time I regenerate the core the example design files return.

Solution

This issue has been fixed in ISE version 14.6.

To work around the issue in ISE 14.5 and earlier, remove the .xci file from the project and add the generated source files or the generated netlist manually to the project once IP customization is complete.
AR# 54732
Date Created 03/04/2013
Last Updated 08/12/2014
Status Active
Type Known Issues
Devices
  • FPGA Device Families
Tools
  • ISE Design Suite