I have an Implemented design.
After running the DRC check or when attempting to generate the Bitstream, I receive the following ERROR message:
How can this be fixed?
The partial antenna message should not happen in any design.
This means there are some nets with endpoints not connected to any PIN, which could cause problems when the design is loaded into the FPGA.
To work around this problem you can try to reroute the nets involved from the Vivado GUI or the Tcl command window.
For the Tcl command window you need to follow the steps bellow:
route_design -unroute -nets [get_nets <net_name>]
route_design -nets [get_nets <net_name>] -effort_level high
report_drc -name <report_name> -rules RTSTAT-5 -verbose
For Vivado GUI steps, please refer to (Xilinx Answer 54683)