Most Revision Control/Version Control systems make checked-in sources read-only. However, when using read-only .XCI Xilinx IP Core files using Vivado in non-project mode, the following errors can be observed:
CRITICAL WARNING: [Designutils 20-1365] Unable to generate target(s) for the following file is locked
WARNING: [IP_Flow 19-2162] IP '...' is locked. Locked reason: IP '...' is write protected.
WARNING: [Common 17-259] Unknown Tcl command
ERROR:sim:709 - Unable to migrate project
ERROR: [IP_Flow 19-98] Generation of the IP CORE failed.
How can I avoid these errors and still use revision control in my Version Control software?
To solve the problem, in the Vivado tool you can manually make the read-only .XCI files writable again, however, this creates problems with the Version Control system.
Another solution is to use the "create_project -in_memory" mode and "unlock" the XCI file:
create_project -in memory
set_property part <part> [current_project]
read_ip <xci file>
set_property is_locked false [get_files <xci file>]
generate_target synthesis [get_files <xci file>]
synth_design -top <top name> -part <part>