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AR# 54912

Block Mem Generator v7.3 - how many clock cycles does the block Ram read port enable signal (ENB) need to assert for to read correct output values


How many clock cycles do I need to assert ENB for in order to read a set of data (n).

I have observed that the last data read from the core is not correct.


Assertion of the ENB signal depends upon core latency.

It is based on the latency needed to assert the enable signal for correct functioning of the core.

Block Memory Generator in an SDP configuration has a minimum latency of 1 clock cycle.

When reading a set of data (n), you need to assert the Enable signal ENB for (n+1) clock cycles.

The Primitive Output Register and Core output Register feature are optional in the core

If you are enabling these features in the core GUI, then to read all (n) data with the Primitive and output register enabled, you need to assert Port B and enable ENB for (n+3) clock cycles.

Below is the equation to find how many clock cycles you need to assert ENB for when reading a set of data (n).

ENB assert clock cycle =  n data + (Primitive Output Register(optional) + Core output Register(optional) + 1 ) latency

AR# 54912
Date 11/21/2014
Status Active
Type General Article
  • FPGA Device Families
  • ISE Design Suite
  • Vivado Design Suite
  • Block Memory Generator