INFO: [Synth 8-637] synthesizing blackbox instance 'U0' of component 'ramsp' [f:/project_1/project_1.srcs/sources_1/ip/ramsp_0/synth/ramsp_0.vhd:91]
INFO: [Synth 8-256] done synthesizing module 'ramsp_0' (1#1) [f:/project_1/project_1.srcs/sources_1/ip/ramsp_0/synth/ramsp_0.vhd:70]
[Opt 31-30] Blackbox U0 (ramsp) is driving pin I of primitive cell dataout_OBUF[0]_inst. This blackbox cannot be found in the existing library.
Why does this occur and how can this be avoided?This can occur when the main file in the IP package is marked as an include file in the IP Packager.
Uncheck this box in the IP Package and re-generate the IP core.
Then remove the original IP core from the previous package from the Vivado project and add a new modified version.
To ensure that this has worked, look at the Sources pane in the Vivado project and expand the IP source.
All sources should be referenced and none should contain a question mark.